XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 17

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
The clock and data recovery (CDR) unit accepts the high speed NRZ serial data from the Differential LVPECL
receiver and generates a clock that is the same frequency as the incoming data. The clock recovery can either
utilize the transmitter’s CMU reference clock from either REFCLKP/N or TTLREFCLK (+/- 20ppm) or it can use
independent clock source CDRAUXREFCLK (+/- 200ppm) to train and monitor its clock recovery PLL. Initially
upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock
onto the incoming receive data stream. Whenever the recovered clock frequency deviates from the local
reference clock frequency by more than approximately ±500 ppm, the clock recovery PLL will switch and lock
back onto the local reference clock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will
continue to supply a receive clock (based on the local reference) to the framer/mapper device. When the
LOSEXT is asserted by the optical module or when LOS is detected, the receive parallel data output will be
forced to a logic zero state for the entire duration that a LOS condition is detected. This acts as a receive data
mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When the
LOSEXT becomes inactive and the recovered clock is determined to be within ±500 ppm accuracy with respect
to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back
onto the incoming receive data stream.
Table 8
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
CMUFREQSEL CDRREFSEL
2.3
2.3.1
REF
REF
1Requires frequency accuracy better than +/- 20 ppm in order for the transmitted data rate frequency
2
N
T
CDRAUXREFCLK requires accuracy of 77.76 MHz +/- 200 ppm.
ABLE
AME
DUTY
to have the necessary accuracy required for SONET systems.
X
X
0
0
1
1
TOL
Receive Clock and Data Recovery
specifies the Clock and Data Recovery Unit performance characteristics.
Internal Clock and Data Recovery Bypass
8: CDR AUXREFCLK R
T
0
0
0
0
1
1
ABLE
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
7: C
Reference clock frequency tolerance
LOCK
Reference clock duty cycle
STS12/
STS3
EFERENCE
0
1
0
1
0
1
D
P
ATA
ARAMETER
Table 7
R
not referenced by CDR
not referenced by CDR
F
ECOVERY UNIT REFERENCE CLOCK SETTINGS
F
REQUENCY
REFCLKP/N
REQUENCY
TTLREFCLK
shows Clock and Data Recovery reference clock settings.
77.76 MHz
77.76 MHz
19.44 MHz
19.44 MHz
17
(MH
R
1
EQUIREMENT
OR
1
Z
)
CDRAUXREFCLK
F
REQUENCY
77.76 MHz
77.76 MHz
F
not used
not used
not used
not used
OR
C
-200
LOCK AND
M
40
(MH
IN
Z
)
2
T
YP
D
F
ATA
REQUENCY
CDR O
XRT91L31
R
+200
M
155.52
622.08
155.52
622.08
155.52
622.08
60
ECOVERY
AX
UTPUT
(MH
U
ppm
NITS
%
Z
)