XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 14

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
The XRT91L31 transceiver is designed to operate with a SONET Framer/ASIC device and provide a high-
speed serial interface to optical networks. The transceiver converts 8-bit parallel data running at 77.76 Mbps
(STS-12/STM-4) or 19.44 Mbps (STS-3/STM-1) to a serial Differential LVPECL bit stream at 622.08 Mbps or
155.52 Mbps and vice-versa. It implements a clock multiplier unit (CMU), SONET/SDH serialization/de-
serialization (SerDes), receive clock and data recovery (CDR) unit and a SONET/SDH frame and byte
boundary detection circuit. The transceiver is divided into Transmit and Receive sections and is used to
provide the front end component of SONET equipment, which includes primarily serial transmit and receive
functions.
Functionality of the transceiver can be configured by using the appropriate signal level on the STS-12/STS-3
pin. STS-3/STM-1 mode is selected by pulling STS-12/STS-3 "Low" as described in the Hardware Pin
Descriptions. However, if STS-12/STM-4 mode is desired, it is selected by pulling STS-12/STS-3 "High."
Therefore, the following sections describe the functionality rather than how each function is controlled. Hence,
the Hardware Pin and Register Bit Descriptions focus on device configuration.
The XRT91L31 can accept both a 19.44 MHz or a 77.76 MHz Differential LVPECL clock input at REFCLKP/N
or a Single-Ended LVTTL clock at TTLREFCLK as its internal timing reference for generating higher speed
clocks. The REFCLKP/N or TTLREFCLK input should be generated from an LVPECL/LVTTL crystal oscillator
which has a frequency accuracy better than 20ppm in order for the transmitted data rate frequency to have the
necessary accuracy required for SONET systems. The reference clock can be provided with one of two
frequencies chosen by CMUFREQSEL. The reference frequency options for the XRT91L31 are listed in
Table 1.
Due to different operating modes and data logic paths through the device, there is an associated latency from
data ingress to data egress.
Serial Remote Loopback
1.0 FUNCTIONAL DESCRIPTION
1.1
1.2
1.3
CMUFREQSEL
Thru-mode
Operation
Mode Of
STS-12/STM-4 and STS-3/STM-1 Mode of Operation
Clock Input Reference for Clock Multiplier (Synthesizer) Unit
Data Latency
0
0
1
1
T
ABLE
3: CMU R
STS12/STS3
MSB at RXIP/N to data on RXDO[7:0]
Table 4
MSB at RXIP/N to MSB at TXOP/N
T
EFERENCE
ABLE
0
1
0
1
4: D
specifies the data latency for a typical path.
Data Path
F
ATA INGRESS TO DATA EGRESS LATENCY
REQUENCY
REFCLKP/N
REFERENCE FREQUENCY
O
14
77.76 MHz
77.76 MHz
19.44 MHz
19.44 MHz
PTIONS
OR
TTLREFCLK
(D
IFFERENTIAL OR
Recoved RXIP/N Clock
Recoved RXIP/N Clock
Clock Reference
S
INGLE
STS-12/STM-4
STS-12/STM-4
STS-3/STM-1
STS-3/STM-1
155.52 Mbps
622.08 Mbps
155.52 Mbps
622.08 Mbps
-E
D
ATA
NDED
Range Of Clock
R
ATE
)
25 to 35
Cycles
2 to 4
REV. 1.0.2