XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 8

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
PIN DESCRIPTION
PIO_CTRL
RLOOPS
DLOOP
ALOOP
N
AME
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVTTL,
LVTTL,
LVTTL,
LVTTL,
L
EVEL
T
YPE
I
I
I
I
P
48
63
62
64
IN
Transmit Parallel Clock Directional Control
Transmit Parallel Clock Output Operation
If this pin is asserted "High", TXPCLK_IO is a parallel bus clock
output. Data on the TXDI[7:0] must be synchronously applied
prior to the sampling by the PISO at the rising edge of
TXPCLK_IO clock output driven by the XRT91L31.
Alternate Transmit Parallel Clock Input Operation
Asserting this control pin "Low" or if left unconnected, it config-
ures TXPCLK_IO to serve as a parallel bus clock input rather
than a parallel bus clock output and permits the XRT91L31 to
accept the external clock input. Data on the TXDI[7:0] is then
sampled at the rising edge of the TXPCLK_IO clock input
driven by the framer/mapper device.
"Low" = TXPCLK_IO is a Parallel Clock Input.
"High" = TXPCLK_IO is a Parallel Clock Output.
N
This pin is provided with an internal pull-down.
Serial Remote Loopback
The serial remote loopback mode interconnects the receive
serial data input to the transmit serial data output. If serial
remote loopback is enabled, the 8-bit parallel transmit data
input is ignored while the 8-bit parallel receive data output is
maintained.
"Low" = Disabled
"High" = Serial Remote Loopback Mode Enabled
N
Digital Local Loopback
The digital local loopback mode interconnects the 8-bit parallel
transmit data input and TxCLK to the 8-bit parallel receive data
output and RxCLK respectively while maintaining the transmit
serial data output. If digital local loopback is enabled, the
receive serial data input is ignored.
"Low" = Disabled
"High" = Digital Local Loopback Mode Enabled
N
Analog Local Loopback
This loopback feature serializes the 8-bit parallel transmit data
input and presents the data to the transmit serial output and in
addition it also internally routes the serialized data back to the
Clock and Data Recovery block for serial to parallel conversion.
The received serial data input is ignored.
"Low" = Disabled
"High" = Analog Local Loopback Mode Enabled
OTE
OTE
OTE
8
: Parallel Clock Input operation has the advantage of
: DLOOP and RLOOPS can be enabled simultaneously
: DLOOP and RLOOPS can be enabled simultaneously
permitting the framer/mapper device timing to be
synchronized with the transceiver transmitter timing.
to achieve a dual loopback diagnostic feature in normal
operation.
to achieve a dual loopback diagnostic feature in normal
operation.
D
ESCRIPTION
REV. 1.0.2