XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 11

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
RECEIVER SECTION
PIN DESCRIPTION
XRXCLKIP
XRXCLKIN
RXPCLKO
CDRAUX-
REFCLK
RXDO0
RXDO1
RXDO2
RXDO3
RXDO4
RXDO5
RXDO6
RXDO7
N
RXIP
RXIN
OOF
AME
Diff LVPECL
Diff LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVTTL,
LVTTL,
LVTTL,
LVTTL,
L
EVEL
T
YPE
O
O
I
I
I
I
P
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
19
20
22
23
24
25
26
27
13
14
29
32
11
8
9
IN
Receive Parallel Data Output
77.76 Mbps (STS-12/STM-4) / 19.44 Mbps (STS-3/STM-1)
8-bit parallel receive data output is updated simultaneously on
the falling edge of the RXPCLKO output. The 8-bit parallel
interface is de-multiplexed from the receive serial data input
MSB first (RXDO[7]). The XRT91L31 will output the data on the
falling edge of RXPCLKO clock.
Receive Serial Data Input
The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is applied to
these input pins. These pins have internal LVPECL common-
mode biasing circuit. External 100R termination is required
between RXIP/N pins.
External Recovered Receive Clock Input
The differential receive serial data stream of 622.08 Mbps
STS-12/STM-1 or 155.52 Mbps STS-3/STM-1 is sampled on
the rising edge of this externally recovered differential clock
coming from the optical module. It is used when the internal
CDR unit is disabled and bypassed by the CDRDIS pin.
These pins have internal LVPECL common-mode biasing cir-
cuit. External 100R termination is required between XRX-
CLKIP/N pins.
N
Receive Parallel Clock Output (77.76 MHz or 19.44 MHz)
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
clock output reference for the 8-bit parallel receive data output
RXDO[7:0]. The parallel received data output bus will be
updated on the falling edge of this clock.
Clock and Data Recovery Auxillary Reference Clock
77.76 MHz ± 200 ppm auxillary reference clock for the CDR.
N
Out of Frame Input Indicator
This level sensitive input pin is used to initiate frame detection
and byte alignment recovery when OOF is declared by the
downstream device. When this pin is held High, FRAME-
PULSE will pulse for a single RXPCLKO period upon the detec-
tion of every third frame alignment A2 byte in the incoming
SONET/SDH Frame.
"Low" = Normal Operation
"High" = OOF Indication initiating frame detection and byte
boundary recovery and activating FRAMEPULSE
OTE
OTE
11
: In the event that XRXCLKIP/N differential input pins are
: In the event that CDRAUXREFCLK LVTTL input pin is
unused, XRXCLKIP should be tied to VCC with a 1k
Ohm pull-up and XRXCLKIN should be tied to Ground
with a 1k Ohm pull-down.
unused, CDRAUXREFCLK should be tied to ground.
D
ESCRIPTION
XRT91L31