XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 20

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
Tx output while the LOSEXT input is set to a “LOW” state. Note that the DLOSDIS control pin has no impact
on the CDR muting function due to LOSEXT. DLOSDIS only applies to muting as a result of DLOS detection.
Also, note that serial muting function (RLPS_D_MUTE) only impacts RLOOPS data going to Tx output.
A Frame and Byte Boundary Detection circuit searches the incoming data channel for three consecutive A1
(0xF6 Hex) bytes followed by three consecutive A2 (0x28 Hex) bytes. The detector operates under the control
of the OOF (Out of Frame) signals provided from the SONET Framer. Detection is enabled when OOF is held
"High" and remains active until OOF goes "Low." When framing pattern detection is enabled, the framing
pattern is used to locate byte and frame boundaries in the incoming receive data stream. The receive serial-to-
parallel converter block uses the located byte boundary to assemble the incoming data stream into bytes for
output on the parallel data output bus RXDO[7:0]. The frame boundary is reported on the frame pulse
(FRAMEPULSE) output at the onset of detecting the third A2 byte pattern when any serial 48-bit pattern
matching the framing pattern is detected on the incoming data stream. While in the pattern search and
detection state and so long is OOF is active, the frame pulse (FRAMEPULSE) output is activated for one byte
clock cycle (RXPCLKO = 12.86 ns pulse duration for STS-12/STM-4 or 51.44 ns pulse duration for STS-3/
STM-1) anytime a 48-bit pattern matching the framing pattern is detected on the incoming data stream. Once
the SONET Framer Overhead Circuitry has verified that frame and byte synchronization are correct, the OOF
input pin should be de-asserted by the SONET Framer to disable the XRT91L31 frame search process from
trying to synchronize repeatedly and to de-activate FRAMEPULSE. When the XRT91L31’s framing pattern
detection is disabled upon the de-assertion of OOF input pin from the SONET Framer, the byte boundary will
lock to the detected location and will remain locked to that location found when detection was previously
enabled.
During STS-12/STM-4 operation, the SIPO is used to convert the 622.08 Mbps serial data input to 77.76 Mbps
parallel data output which can interface to a SONET Framer/ASIC. If the XRT91L31 is operating in STS-3/
STM-1, the SIPO will convert the 155.52 Mbps serial data input to 19.44 Mbps parallel data output. The SIPO
bit de-interleaves the serial data input into an 8-bit parallel output to RXDO[7:0]. A simplified block diagram is
shown in
F
2.6
2.7
IGURE
8. S
SONET Frame Boundary Detection and Byte Alignment Recovery
Receive Serial Input to Parallel Output (SIPO)
RXPCLKO
RXDO n+
RXDO7
Figure
RXDO0
RXDO n
IMPLIFIED
8. XRT91L31 clocks data out on RXDO[7:0] at the falling edge of RXPCLKO.
8-bit Parallel LVTTL Output Data
B
LOCK
b
b
b
b
n+
0
n
7
3
3
3
3
D
b
b
b
b
n+
IAGRAM OF
0
n
7
2
2
2
2
b
b
b
b
n+
0
n
7
1
1
1
1
b
b
b
b
n+
0
n
7
0
0
0
0
77.76 MHz (STS-12/STM-4) or 19.44 MHz (STS-3/STM-1)
SIPO
b
20
7
3
b
6
3
b
5
3
b
4
3
155.52 Mbps STS-3/STM-1 serial data rate
b
3
3 b
622.08 Mbps STS-12/STM-4 or
2
3 b
1
3
b
7
0 b
6
0 b
5
0 b
4
0
b
3
0 b
2
0 b
1
0 b
0
0
RXIP/N
REV. 1.0.2