XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 15

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
The receive section of XRT91L31 include the inputs RXIP/N, followed by the clock and data recovery unit
(CDR) and receive serial-to-parallel converter. The receiver accepts the high speed Non-Return to Zero (NRZ)
serial data at 622.08 Mbps or 155.52 Mbps through the input interfaces RXIP/N. The clock and data recovery
unit recovers the high-speed receive clock from the incoming scrambled NRZ data stream. The recovered
serial data is converted into an 8-bit-wide, 77.76 Mbps or 19.44 Mbps parallel data and presented to the
RXDO[7:0] parallel interface. This parallel interface is designed for Single-Ended LVTTL operation. A divide-
by-8 version of the high-speed recovered clock RXPCLKOP/N, is used to synchronize the transfer of the 8-bit
RXDO[7:0] data with the receive portion of the framer/mapper device. Upon initialization or loss of signal or
loss of lock, the external reference clock signal of 19.44 MHz or 77.76 MHz is used to start-up the clock
recovery phase-locked loop for proper operation. In certain applications, the CDR block on the XRT91L31 can
be disabled and bypassed by enabling the CDRDIS pin to permit the flexibility of using an externally recovered
receive clock thru the XRXCLKIP/N pins.
The receive serial inputs are applied to RXIP/N and originate from an AC coupled environement (i.e. AC-
coupled SFP). A simplified block diagram is shown in
down biasing resitors, a 100
close to the RXI pins as possible. See Applications note for further clarifications.
F
2.0 RECEIVE SECTION
2.1
IGURE
3. R
Receive Serial Input
ECEIVE
STS-12/ STM-4
STS-3/ STM-1
XRT91L31
Transceiver
XRXCLKIN
XRXCLKIP
or
S
RXIP
RXIN
ERIAL
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
I
NPUT
Ω
( optional )
100 Ohm
line-to-line termination is the only resistor needed and must be installed as
I
NTERFACE
Install terminators close to
RXIP and RXIN pins
1k
1k
B
LOCK
Tie unused differential input pins
to VCC and GND
15
Internally AC coupled
Figure
SFP , Optical Module
3. Since this dievice has internal pull up/pull
Optical Fiber
XRT91L31