XRT91L31IQTR-F Exar Corporation, XRT91L31IQTR-F Datasheet - Page 29

• Manufacturer Part Number: XRT91L31IQTR-F
• Description: SONET SDH - 8 Bit OC12/STM4, OC3/STM1 PHY Transceiver (with Improved Jitter Transfer Used For Loop Timing Applications)
• Manufacturer: Exar Corporation
• Type: Transceiverr

Specifications of XRT91L31IQTR-F

• Input: LVCMOS, LVPECL, LVTTL
• Output: LVCMOS, LVPECL, LVTTL
• Frequency - Max: 77.76MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-FQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.2
Two types of loop timing are possible in the XRT91L31.
In the internal loop timing mode, loop timing is controlled by the LOOPTIME pin. This mode is selected by
asserting the LOOPTIME signal to a high level. When the loop timing mode is activated, the CMU synthesized
hi-speed reference clock input to the Retimer is replaced with the hi-speed internally recovered receive clock
coming from the CDR. Under this condition both the transmit and receive sections are synchronized to the
internally recovered receive clock. Loop time mode directly locks the Retimer to the recovered receive clock.
In external loop timing mode, the XRT91L31 allows the user the flexibility of using an externally recovered
receive clock for retiming the high speed serial data. First, the CDRDIS input pin should be set high. By doing
so, the internal CDR is disabled and bypassed and the XRT91L31 will sample the incoming high speed serial
data on RXIP/N with the externally recovered receive clock connected to the XRXCLKIP/N inputs. In this state,
the receive clock de-jittering and recovery is done externally and fed thru XRXCLKIP/N and the XRT91L31 will
sample RXIP/N on the rising edge of XRXCLKIP/N. Secondly, the LOOPTIME pin must also be set high in
order to select the externally recovered receive clock on XRXCLKIP/N as the reference clock source for the
transmit serial data output stream TXOP/N.
Table 17
CDR or an external recovered clock in loop timing applications is shown in
3.7
CDRDIS
Loop Timing and Clock Control
0
0
1
1
provides configuration for selecting the loop timing and clock recovery modes. The use of the on-chip
LOOPTIME
T
ABLE
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
0
1
0
1
17: L
OOP
External CDR thru XRXCLKIP/N
T
IMING AND
T
RANSMIT
Clock Multiplier Unit
Clock Multiplier Unit
Internal CDR
C
C
LOCK
LOCK
29
S
OURCE
R
ECOVERY CONFIGURATIONS
622.08/155.52 Mbps data on RXIP/N sam-
622.08/155.52 Mbps data on RXIP/N sam-
Clock and Data recovery by internal CDR
Externally recovered Receive Clock from
Externally recovered Receive Clock from
Clock and Data recovery by internal CDR
pled at rising edge of XRXCLKIP/N
pled at rising edge of XRXCLKIP/N
Figure
R
ECEIVE
CDR Disabled.
CDR Disabled.
CDR Enabled.
CDR Enabled.
16.
XRXCLKIP/N
XRXCLKIP/N
C
LOCK
S
OURCE
XRT91L31