SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 10

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
7.4 Hi-Speed USB analog transceivers
7.5 Power management
7.6 Phase-Locked Loop (PLL)
7.7 Power-On Reset (POR)
The EHCI is responsible for the port-routing switching mechanism. Two register bits are
used for ownership switching. During power-on and system reset, the default ownership of
all downstream ports is the OHCI. The Enhanced Host Controller Driver (EHCD) controls
the ownership during normal functionality.
The Hi-Speed USB analog transceivers directly interface to the USB cables through
integrated termination resistors. These transceivers can transmit and receive serial data
at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s).
The SAF1562HL provides an advanced power management capability interface that is
compliant with PCI Bus Power Management Interface Specification Rev. 1.1. Power is
controlled and managed by the interaction between drivers and PCI registers.
For a detailed description on power management, see
A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows
the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components
are required for the PLL to operate.
Figure 3
The internal Power-On Reset Pulse (PORP) starts at t0 and follows the curve of V
V
(maximum 1.4 V) and a delay element will add another t
the PORP drops to LOW. If the dip at t4 to t5 is too short (less than or equal 11 μs), the
PORP will not react and will remain LOW. A HIGH on PORP will be generated whenever
V
V
from 0 V to 3.3 V with the rise time between 5 ms and 11 ms.
Fig 3.
REG1V8
AUX1V8
I(VAUX3V3)
(1) PORP = internal power-on reset pulse.
, V
until t1. At t1, the detector will detect the passing of the trip level V
shows a possible curve of V
Power-on reset
t0
, V
REG1V8
t
t1
PORP
CC(I/O)
All information provided in this document is subject to legal disclaimers.
drops below V
, V
Rev. 2 — 24 November 2010
I(VREG3V3)
and V
trip(L)
t2
>11 μs
Hi-Speed Universal Serial Bus PCI Host Controller
AUX1V8
(minimum 0.95 V) for more than 11 μs. The
CC(I/O)_AUX
, V
t
t3
PORP
REG1V8
during power on should ramp up linearly
with dips at t2 to t3 and t4 to t5.
Section
PORP
t4
≤11 μs
(minimum 200 ns) before
t5
10.
SAF1562
© NXP B.V. 2010. All rights reserved.
trip(H)
V
V
V
V
PORP
AUX1V8
REG1V8
trip(H)
trip(L)
008aaa244
(1)
AUX1V8
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