SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 59

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
11.1.22 HcRhPortStatus[4:1] register
The HcRhPortStatus[4:1] register is used to control and report port events on a per-port
basis. Number Downstream Ports represents the number of HcRhPortStatus registers
that are implemented in hardware. The lower word reflects the port status. The upper
word reflects the status change bits. Some status bits are implemented with special write
behavior. If a transaction—token through handshake—is in progress when a write to
change port status occurs, the resulting port status change is postponed until the
transaction completes. Always write logic 0 to the reserved bits. The bit allocation of the
register is given in
Table 84.
Address: Content of the base address register + 54h
[1]
Table 85.
Address: Content of the base address register + 54h
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 21 reserved
20
19
The reserved bits should always be written with the reset value.
Symbol
PRSC
OCIC
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
allocation
HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
description
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
All information provided in this document is subject to legal disclaimers.
Table
reserved
reserved
Description
-
Port Reset Status Change: This bit is set at the end of the 10 ms port reset
signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no
effect.
0 — Port reset is not complete
1 — Port reset is complete
Port Over Current Indicator Change: This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when the Root
Hub changes the POCI (Port Over Current Indicator) bit. The HCD can write
logic 1 to clear this bit. Writing logic 0 has no effect.
0 — No change in POCI
1 — POCI has changed
Rev. 2 — 24 November 2010
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
84.
[1]
[1]
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
reserved
Hi-Speed Universal Serial Bus PCI Host Controller
PRSC
R/W
R/W
R/W
PRS
R/W
[1]
28
20
12
0
0
0
4
0
reserved
OCIC
POCI
R/W
R/W
R/W
R/W
[1]
27
19
11
0
0
0
3
0
PSSC
R/W
R/W
R/W
PSS
R/W
26
18
10
0
0
0
2
0
SAF1562
© NXP B.V. 2010. All rights reserved.
PESC
LSDA
PES
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
59 of 121
CSC
CCS
R/W
R/W
PPS
R/W
R/W
24
16
0
0
8
0
0
0