SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 67

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
Table 93.
Address: Content of the base address register + 20h
Bit
31 to 24
23 to 16
15 to 8
7
6
Symbol
reserved
ITC[7:0]
reserved
LHCR
IAAD
USBCMD - USB Command register bit description
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2010
Description
-
Interrupt Threshold Control: Default = 08h. This field is used by the
system software to select the maximum rate at which the Host Controller
will issue interrupts. If software writes an invalid value to this register, the
results are undefined. Valid values are:
00h — reserved
01h — 1 micro frame
02h — 2 micro frames
04h — 4 micro frames
08h — 8 micro frames (equals 1 ms)
10h — 16 micro frames (equals 2 ms)
20h — 32 micro frames (equals 4 ms)
40h — 64 micro frames (equals 8 ms)
Software modifications to this field while HCH (bit 12) in the USBSTS
register is zero results in undefined behavior.
-
Light Host Controller Reset: This control bit is not required. It allows the
driver software to reset the EHCI controller, without affecting the state of
the ports or the relationship to the companion Host Controllers. If not
implemented, a read of this field will always return zero. If implemented,
on read:
0 — Indicates that the Light Host Controller Reset has completed and it is
ready for the host software to reinitialize the Host Controller
1 — Indicates that the Light Host Controller Reset has not yet completed
Interrupt on Asynchronous Advance Doorbell: This bit is used as a
doorbell by software to notify the Host Controller to issue an interrupt the
next time it advances the asynchronous schedule. Software must write
logic 1 to this bit to ring the doorbell. When the Host Controller has evicted
all appropriate cached schedule states, it sets IAA (bit 5 in the USBSTS
register). If IAAE (bit 5 in the USBINTR register) is logic 1, then the Host
Controller will assert an interrupt at the next interrupt threshold. The Host
Controller sets this bit to logic 0 after it sets IAA. Software should not set
this bit when the asynchronous schedule is inactive because this results in
an undefined value.
Hi-Speed Universal Serial Bus PCI Host Controller
SAF1562
© NXP B.V. 2010. All rights reserved.
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