SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 116

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 54. HcHCCA - Host Controller Communication Area
Table 55. HcHCCA - Host Controller Communication Area
Table 56. HcPeriodCurrentED - Host Controller Period
Table 57. HcPeriodCurrentED - Host Controller Period
Table 58. HcControlHeadED - Host Controller Control Head
Table 59. HcControlHeadED - Host Controller Control Head
Table 60. HcControlCurrentED - Host Controller Control
Table 61. HcControlCurrentED - Host Controller Control
Table 62. HcBulkHeadED - Host Controller Bulk Head
Table 63. HcBulkHeadED - Host Controller Bulk Head
Table 64. HcBulkCurrentED - Host Controller Bulk Current
Table 65. HcBulkCurrentED - Host Controller Bulk Current
Table 66. HcDoneHead - Host Controller Done Head
Table 67. HcDoneHead - Host Controller Done Head
Table 68. HcFmInterval - Host Controller Frame Interval
Table 69. HcFmInterval - Host Controller Frame Interval
Table 70. HcFmRemaining - Host Controller Frame
Table 71. HcFmRemaining - Host Controller Frame
Table 72. HcFmNumber - Host Controller Frame Number
Table 73. HcFmNumber - Host Controller Frame Number
Table 74. HcPeriodicStart - Host Controller Periodic Start
Table 75. HcPeriodicStart - Host Controller Periodic Start
Table 76. HcLSThreshold - Host Controller LS Threshold
SAF1562
Product data sheet
Disable register bit description . . . . . . . . . . . . .44
register bit allocation . . . . . . . . . . . . . . . . . . . .45
register bit description . . . . . . . . . . . . . . . . . . .45
Current Endpoint Descriptor register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Current Endpoint Descriptor register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Endpoint Descriptor register bit allocation . . . .46
Endpoint Descriptor register bit description . . .47
Current Endpoint Descriptor register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Current Endpoint Descriptor register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Endpoint Descriptor register bit allocation . . . .48
Endpoint Descriptor register bit description . . .48
Endpoint Descriptor register bit allocation . . . .49
Endpoint Descriptor register bit description . . .49
register bit allocation . . . . . . . . . . . . . . . . . . . .50
register bit description . . . . . . . . . . . . . . . . . . .50
register bit allocation . . . . . . . . . . . . . . . . . . . .50
register bit description . . . . . . . . . . . . . . . . . . .51
Remaining register bit allocation . . . . . . . . . . .51
Remaining register bit description . . . . . . . . . .52
register bit allocation . . . . . . . . . . . . . . . . . . . .52
register bit description . . . . . . . . . . . . . . . . . . .53
register bit allocation . . . . . . . . . . . . . . . . . . . .53
register bit description . . . . . . . . . . . . . . . . . . .54
register bit allocation . . . . . . . . . . . . . . . . . . . .54
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2010
Table 77. HcLSThreshold - Host Controller LS Threshold
Table 78. HcRhDescriptorA - Host Controller Root Hub
Table 79. HcRhDescriptorA - Host Controller Root Hub
Table 80. HcRhDescriptorB - Host Controller Root Hub
Table 81. HcRhDescriptorB - Host Controller Root Hub
Table 82. HcRhStatus - Host Controller Root Hub Status
Table 83. HcRhStatus - Host Controller Root Hub Status
Table 84. HcRhPortStatus[4:1] - Host Controller Root Hub
Table 85. HcRhPortStatus[4:1] - Host Controller Root Hub
Table 86. CAPLENGTH/HCIVERSION - Capability
Table 87. CAPLENGTH/HCIVERSION - Capability
Table 88. HCSPARAMS - Host Controller Structural
Table 89. HCSPARAMS - Host Controller Structural
Table 90. HCCPARAMS - Host Controller Capability
Table 91. HCCPARAMS - Host Controller Capability
Table 92. USBCMD - USB Command register bit
Table 93. USBCMD - USB Command register bit
Table 94. USBSTS - USB Status register bit allocation . 69
Table 95. USBSTS - USB Status register bit description 69
Table 96. USBINTR - USB Interrupt Enable register
Table 97. USBINTR - USB Interrupt Enable register
Table 98. FRINDEX - Frame Index register bit allocation 72
Table 99. FRINDEX - Frame Index register
Table 100. PERIODICLISTBASE - Periodic Frame List Base
Table 101. PERIODICLISTBASE - Periodic Frame List Base
Table 102. ASYNCLISTADDR - Current Asynchronous List
Hi-Speed Universal Serial Bus PCI Host Controller
register bit description . . . . . . . . . . . . . . . . . . . 54
Descriptor A register bit allocation . . . . . . . . . 55
Descriptor A register bit description . . . . . . . . 55
Descriptor B register bit allocation . . . . . . . . . 56
Descriptor B register bit description . . . . . . . . 57
register bit allocation . . . . . . . . . . . . . . . . . . . . 57
register bit description . . . . . . . . . . . . . . . . . . . 58
Port Status[4:1] register bit allocation . . . . . . . 59
Port Status[4:1] register bit description . . . . . . 59
Registers Length/Host Controller Interface
Version Number register bit allocation . . . . . . 63
Registers Length/Host Controller Interface
Version Number register bit description . . . . . 63
Parameters register bit allocation . . . . . . . . . . 63
Parameters register bit description . . . . . . . . . 64
Parameters register bit allocation . . . . . . . . . . 65
Parameters register bit description . . . . . . . . . 65
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 71
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 71
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 73
Address register bit allocation . . . . . . . . . . . . . 73
Address register bit description . . . . . . . . . . . . 74
Address register bit allocation . . . . . . . . . . . . . 74
SAF1562
© NXP B.V. 2010. All rights reserved.
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