SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 75

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
11.3.7 CONFIGFLAG register
Table 103. ASYNCLISTADDR - Current Asynchronous List Address register bit description
Address: Content of the base address register + 38h
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in
Table 104. CONFIGFLAG - Configure Flag register bit allocation
Address: Value read from func2 of address 10h + 60h
[1]
Table 105. CONFIGFLAG - Configure Flag register bit description
Address: Value read from func2 of address 10h + 60h
Bit
31 to 5
4 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 1
0
The reserved bits should always be written with the reset value.
Symbol
reserved
CF
Symbol
LPL[26:0]
reserved
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
All information provided in this document is subject to legal disclaimers.
Description
-
Configure Flag: The host software sets this bit as the last action in its
process of configuring the Host Controller. This bit controls the default
port-routing control logic.
0 — Port-routing control logic default-routes each port to an implementation
dependent classic Host Controller
1 — Port-routing control logic default-routes all ports to this Host Controller
Rev. 2 — 24 November 2010
R/W
R/W
R/W
R/W
Description
Link Pointer List: These bits correspond to memory address signals
31 to 5, respectively. This field may only reference a Queue Head (QH).
-
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
reserved
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
reserved
[1]
R/W
R/W
R/W
R/W
[1]
[1]
[1]
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
SAF1562
© NXP B.V. 2010. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
Table
104.
75 of 121
R/W
R/W
R/W
R/W
CF
24
16
0
0
8
0
0
0