SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 48

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
11.1.11 HcBulkHeadED register
Table 61.
Address: Content of the base address register + 24h
This register (see
Table 62.
Address: Content of the base address register + 28h
[1]
Table 63.
Address: Content of the base address register + 28h
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
The reserved bits should always be written with the reset value.
Symbol
CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving
reserved
HcControlCurrentED - Host Controller Control Current Endpoint Descriptor
register bit description
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit
allocation
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit
description
R/W
R/W
R/W
R/W
Symbol
BHED[27:0]
reserved
31
23
15
0
0
0
7
0
All information provided in this document is subject to legal disclaimers.
Table
Rev. 2 — 24 November 2010
Description
the present. The Host Controller must continue processing the list from
where it left off in the last frame. When it reaches the end of the control list,
the Host Controller checks CLF (bit 1 of HcCommandStatus). If set, it
copies the content of HcControlHeadED to HcControlCurrentED and
clears the bit. If not set, it does nothing. The HCD is allowed to modify this
register only when CLE (bit 4 in the HcControl register) is cleared. When
set, the HCD only reads the instantaneous value of this register. Initially,
this is set to logic 0 to indicate the end of the control list.
-
R/W
R/W
R/W
R/W
30
22
14
62) contains the physical address of the first ED of the bulk list.
0
0
0
6
0
BHED[3:0]
Description
Bulk Head ED: The Host Controller traverses the bulk list starting
with the HcBulkHeadED pointer. The content is loaded from HCCA
during the initialization of the Host Controller.
-
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
28
20
12
BHED[27:20]
BHED[19:12]
0
0
0
4
0
BHED[11:4]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
reserved
SAF1562
© NXP B.V. 2010. All rights reserved.
R/W
R/W
R/W
R/W
[1]
25
17
0
0
9
0
1
0
48 of 121
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0