SAF1562HL NXP [NXP Semiconductors], SAF1562HL Datasheet
SAF1562HL
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SAF1562HL Summary of contents
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... Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux. The SAF1562HL directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2 . ...
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... Set-Top Box (STB) I Web appliances 4. Ordering information Table 1. Ordering information Type number Package Name SAF1562HL LQFP100 SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller aux(3V3) Description plastic low profile quad flat package; 100 leads; body 14 Rev. 01 — 7 February 2007 ...
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... V POR CC(I/O) 55, 71 VOLTAGE 18, 43, 58 REGULATOR REG1V8 V CC(I/ I(VREG3V3) DETECT 74 XTAL1 XOSC 75 PLL XTAL2 Fig 1. Block diagram of SAF1562HL SCL SDA 96 GLOBAL CONTROL SAF1562HL OHCI OHCI (FUNCTION 0) (FUNCTION 1) RAM RAM PORT ROUTER CORE RESET_N ATX1 V CC ORIGINAL Hi-SPEED ORIGINAL CORE USB ATX ...
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... V I(VREG3V3) GNDA 17 REG1V8 18 GNDD 19 20 AD[26] AD[25] 21 AD[24 C/BE#[3] 24 IDSEL V 25 CC(I/O) Fig 2. Pin configuration for LQFP100 SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller SAF1562HL Rev. 01 — 7 February 2007 SAF1562 75 XTAL2 74 XTAL1 73 AUX1V8 72 GNDA 71 V CC(I/O) 70 AD[0] 69 AD[1] 68 AD[2] 67 AD[3] 66 AD[4] 65 AD[5] ...
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NXP Semiconductors 6.2 Pin description Table 2. Symbol GNDA AUX1V8 V I(VAUX3V3) INTA# RST# GNDD PCICLK GNT# REQ# AD[31] V CC(I/O) AD[30] AD[29] AD[28] AD[27] V I(VREG3V3) GNDA REG1V8 GNDD AD[26] AD[25] AD[24] SAF1562_1 Product data sheet Hi-Speed Universal Serial ...
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NXP Semiconductors Table 2. Symbol C/BE#[3] IDSEL V CC(I/O) AD[23] AD[22] AD[21] AD[20] AD[19] AD[18] GNDD AD[17] AD[16] C/BE#[2] FRAME# IRDY# TRDY# DEVSEL# V CC(I/O) STOP# CLKRUN# SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller Pin description ...
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NXP Semiconductors Table 2. Symbol REG1V8 PERR# SERR# GNDA PAR C/BE#[1] GNDD AD[15] AD[14] AD[13] AD[12] AD[11] V CC(I/O) AD[10] AD[9] REG1V8 AD[8] C/BE#[0] GNDA AD[7] AD[6] SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller Pin description ...
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NXP Semiconductors Table 2. Symbol GNDD AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] V CC(I/O) GNDA AUX1V8 XTAL1 XTAL2 GNDD V CC(I/O)_AUX OC1_N PWE1_N GNDA RREF GNDA DM1 GNDA DP1 V DDA_AUX OC2_N PWE2_N GNDA SAF1562_1 Product data sheet Hi-Speed Universal ...
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NXP Semiconductors Table 2. Symbol DM2 GNDA DP2 V DDA_AUX GNDD GNDD SCL SDA V CC(I/O)_AUX PME# V CC(I/O)_AUX [1] Symbol names ending with # represent active LOW signals for PCI pins, for example: NAME#. Symbol names ending with underscore ...
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... Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). 7.5 Power management The SAF1562HL provides an advanced power management capability interface that is compliant with PCI Bus Power Management Interface Specification Rev. 1.1 . Power is controlled and managed by the interaction between drivers and PCI registers. ...
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... PCI interrupt signal INTA#. These functions provide memory-mapped, addressable operational registers as required in Open Host Controller Interface Specification for USB Rev. 1.0a and Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 . SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller SAF1562HL V I(VREG3V3 CC(I/O) 11, 25, ...
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... PCI initiator and target A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI transactions as a slave. In the case of the SAF1562HL, the two Open Host Controllers and the Enhanced Host Controller function as both initiators or targets of PCI transactions issued by the host CPU. ...
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NXP Semiconductors Table 3. PCI configuration space registers of OHCI1, OHCI2 and EHCI Address Bits Bits 08h Class Code[23:0] 0Ch reserved Header Type[7:0] 10h Base Address 0[31:0] 14h 18h 1Ch 20h 24h 28h 2Ch ...
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NXP Semiconductors Table 4. Legend: * reset value Bit 8.2.1.2 Device ID register This read-only register that identifies a particular device. The identifier is allocated by NXP Semiconductors. Table 5. Legend: * reset ...
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NXP Semiconductors Table 7. Bit SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller Command register (address 04h) bit description Symbol Description reserved - FBBE Fast Back-to-Back Enable: ...
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NXP Semiconductors Table 7. Bit 8.2.1.4 Status register The Status register read-only register used to record status information on PCI bus-related events. For bit allocation, see Table 8. Bit Symbol Reset Access Bit ...
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NXP Semiconductors Table 9. Bit 10 and 9 DEVSELT 8.2.1.5 Revision ID register This 1 B read-only register indicates a device-specific revision identifier. The value is chosen by the vendor. This field ...
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NXP Semiconductors The Class Code register is divided into three byte-size fields. The upper byte is a base class code that broadly classifies the type of function the device performs. The middle byte is a sub-class code that identifies more ...
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NXP Semiconductors Table 13. Legend: * reset value Bit CLS[7:0] 8.2.1.8 Latency Timer register This register specifies—in units of PCI bus clocks—the value of the Latency Timer for the PCI bus master. Table 14. Legend: * reset ...
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... DCh* Capabilities Pointer: EHCI efficiently manages power using this register. This Power Management register is allocated at offset DCh. Only one Host Controller is needed to manage power in the SAF1562HL. Rev. 01 — 7 February 2007 Description Base Address to Memory-Mapped Host Controller Register Space: The memory size required by OHCI and EHCI are 4 kB and 256 B, respectively ...
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... Value [1] R 0Xh* [7:0] Rev. 01 — 7 February 2007 Table Description Interrupt Line: Indicates which IRQ is used to report interrupt from the SAF1562HL. Table 22. Description Interrupt Pin: INTA# is the default interrupt pin used by the SAF1562HL. Table 23. Description Min_Gnt used to specify how long a burst period the device needs, assuming a clock rate of 33 MHz ...
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NXP Semiconductors Table 24. Legend: * reset value Bit MAX_LAT [ 2Ah for OHCI1 and OHCI2 10h for EHCI. 8.2.1.17 TRDY time-out register This is a read and write register at address 40h. ...
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NXP Semiconductors Table 26. Legend: * reset value Bit 8.2.2.2 FLADJ register This feature is used to adjust any offset from the clock source that generates the clock that drives the SOF counter. When a new value ...
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NXP Semiconductors affect the actual operation of the EHCI Host Controller. The system-specific policy can be established by BIOS initializing this register to a system-specific value. The system software uses the information in this register when enabling devices and ports ...
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NXP Semiconductors Table 32. Address: Value read from address 34h + 1h Legend: * reset value Bit NEXT_ITEM_ 8.2.3.3 PMC register The Power Management Capabilities (PMC) register register, and the bit allocation is ...
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NXP Semiconductors Table 34. Address: Value read from address 34h + 2h Bit 8.2.3.4 PMCSR register The Power Management Control/Status Register (PMCSR register used to manage the ...
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NXP Semiconductors Table 35. Address: Value read from address 34h + 4h Bit Symbol Reset Access Bit Symbol Reset Access [1] Sticky bit, if the function supports PME# from D3 system boot the function does not ...
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NXP Semiconductors Table 36. Address: Value read from address 34h + 4h Bit and 0 8.2.3.5 PMCSR_BSE register The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI bridge-specific functionality and is required for all ...
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NXP Semiconductors Table 38. Address: Value read from address 34h + 6h Bit Table 39. Originating device’s bridge PM state hot D3 cold 8.2.3.6 Data register The Data register is an ...
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... LOW level on SDA during the ninth clock pulse on SCL. For detailed information, refer to The I 9.2 Hardware connections The SAF1562HL can be connected to an external EEPROM through the I interface. The hardware connections are shown in Fig 5. EEPROM connection diagram SAF1562_1 Product data sheet ...
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... NXP Semiconductors The slave address that the SAF1562HL uses to access the EEPROM is 1010 000b. Page mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must be connected to ground (logic 0). 9.3 Information loading from EEPROM Figure 6 default values of Device ID, Vendor ID, subsystem VID and subsystem DID assigned to NXP Semiconductors by PCI-SIG will be loaded ...
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NXP Semiconductors 10.2 USB bus states Reset state — When the USB bus is in the reset state, the USB system is stopped. Operational state — When the USB bus is in the active state, the USB system is operating ...
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... Reset values that are highlighted—for example, 0—are the SAF1562HL implementation-specific reset values; and reset values that are not highlighted—for example, 0—are compliant with OHCI and EHCI specifications. For the OHCI Host Controller, there are only operational registers for the USB operation. ...
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NXP Semiconductors Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 0 Access R Table 43. HcRevision - Host Controller Revision register bit description Address: Value read from func0 or func1 of address 10h + 00h Bit Symbol ...
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NXP Semiconductors Table 45. Address: Value read from func0 or func1 of address 10h + 04h Bit and 6 5 SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller HcControl - ...
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NXP Semiconductors Table 45. Address: Value read from func0 or func1 of address 10h + 04h Bit and 0 11.1.3 HcCommandStatus register The HcCommandStatus register is used by the Host Controller to receive commands issued by ...
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NXP Semiconductors Table 46. Address: Value read from func0 or func1 of address 10h + 08h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written ...
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NXP Semiconductors Table 47. Bit 11.1.4 HcInterruptStatus register This register that provides the status of the events that cause hardware interrupts. The bit allocation of the register is given in Controller sets the ...
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NXP Semiconductors Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 49. Address: Value read from func0 or func1 of address 10h + 0Ch ...
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NXP Semiconductors 11.1.5 HcInterruptEnable register Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. A hardware interrupt is requested ...
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NXP Semiconductors Table 51. Bit 11.1.6 HcInterruptDisable register Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable ...
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NXP Semiconductors Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 53. Address: Value read from func0 or func1 of address 10h + 14h Bit ...
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NXP Semiconductors 11.1.7 HcHCCA register The HcHCCA register contains the physical address of the Host Controller Communication Area (HCCA). The bit allocation is given in determines the alignment restrictions by writing all ones to HcHCCA and reading the content of ...
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NXP Semiconductors Table 56. Address: Value read from func0 or func1 of address 10h + 1Ch Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Table 57. Address: Value read from func0 or ...
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NXP Semiconductors Bit Symbol Reset Access Bit Symbol Reset Access Table 59. Address: Value read from func0 or func1 of address 10h + 20h Bit 11.1.10 HcControlCurrentED register The HcControlCurrentED register contains the physical ...
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NXP Semiconductors Table 61. Address: Value read from func0 or func1 of address 10h + 24h Bit 11.1.11 HcBulkHeadED register This register (see Table 62. Address: Value read from func0 or func1 of address ...
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NXP Semiconductors 11.1.12 HcBulkCurrentED register This register contains the physical address of the current endpoint of the bulk list. The endpoints are ordered according to their insertion to the list because the bulk list must be served in a round-robin ...
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NXP Semiconductors Table 66. Address: Value read from func0 or func1 of address 10h + 30h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written ...
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NXP Semiconductors Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 69. Address: Value read from func0 or func1 of address 10h + 34h ...
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NXP Semiconductors Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 71. Address: Value read from func0 or func1 of address 10h + 38h Bit ...
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NXP Semiconductors Bit Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 73. Address: Value read from func0 or func1 of address 10h + 3Ch Bit 11.1.17 ...
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NXP Semiconductors Table 75. Address: Value read from func0 or func1 of address 10h + 40h Bit 11.1.18 HcLSThreshold register This register contains an 11-bit value used by the Host Controller to determine whether ...
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NXP Semiconductors 11.1.19 HcRhDescriptorA register This register is the first of two registers describing the characteristics of the Root Hub. Reset values are implementation-specific. Table 78 Table 78. Address: Value read from func0 or func1 of address 10h + 48h ...
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NXP Semiconductors Table 79. Address: Value read from func0 or func1 of address 10h + 48h Bit 11.1.20 HcRhDescriptorB register The HcRhDescriptorB register is the second of two registers describing the characteristics of the ...
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NXP Semiconductors Bit Symbol Reset Access Table 81. Address: Value read from func0 or func1 of address 10h + 4Ch Bit PPCM 11.1.21 HcRhStatus register This register is divided into two parts. The lower ...
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NXP Semiconductors Bit Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 83. Address: Value read from func0 or func1 of address 10h + 50h Bit reserved 17 16 ...
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NXP Semiconductors 11.1.22 HcRhPortStatus[4:1] register The HcRhPortStatus[4:1] register is used to control and report port events on a per-port basis. Number Downstream Ports represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word reflects the port ...
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NXP Semiconductors Table 85. Address: Value read from func0 or func1 of address 10h + 54h Bit reserved 9 SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller HcRhPortStatus[4:1] - Host Controller ...
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NXP Semiconductors Table 85. Address: Value read from func0 or func1 of address 10h + 54h Bit SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller HcRhPortStatus[4:1] - Host Controller Root Hub ...
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NXP Semiconductors Table 85. Address: Value read from func0 or func1 of address 10h + 54h Bit 11.2 EHCI controller capability registers Other than the OHCI Host Controller, there are some registers in EHCI that define the ...
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NXP Semiconductors Table 86. Address: Value read from func2 of address 10h + 00h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Table 87. Address: Value read from func2 of address 10h ...
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NXP Semiconductors Bit Symbol Reset Access Bit Symbol Reset Access Table 89. Address: Value read from func2 of address 10h + 04h Bit and ...
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NXP Semiconductors 11.2.3 HCCPARAMS register The Host Controller Capability Parameters (HCCPARAMS) register register, and the bit allocation is given in Table 90. Address: Value read from func2 of address 10h + 08h Bit Symbol Reset Access ...
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NXP Semiconductors 11.2.4 HCSP-PORTROUTE register The HCSP-PORTROUTE (Companion Port Route Description) register is an optional read-only field that is valid only if PRR (bit 7 in the HCSPARAMS register) is logic 1. Its address is value read from func2 of ...
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NXP Semiconductors Table 93. Address: Value read from func2 of address 10h + 20h Bit SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller USBCMD - USB ...
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NXP Semiconductors Table 93. Address: Value read from func2 of address 10h + 20h Bit and 11.3.2 USBSTS register The USB Status (USBSTS) register indicates pending interrupts and various states of the Host Controller. ...
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NXP Semiconductors Table 94. Address: Value read from func2 of address 10h + 24h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written with the ...
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NXP Semiconductors Table 95. Address: Value read from func2 of address 10h + 24h Bit 11.3.3 USBINTR register The USB Interrupt Enable (USBINTR) register enables and disables reporting of the corresponding ...
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NXP Semiconductors Table 96. Address: Value read from func2 of address 10h + 28h Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access [1] The reserved bits should always be written with the ...
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NXP Semiconductors 11.3.4 FRINDEX register The Frame Index (FRINDEX) register is used by the Host Controller to index into the periodic frame list. The register updates every 125 s—once each micro frame. Bits are used to select ...
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NXP Semiconductors Table 99. Address: Value read from func2 of address 10h + 2Ch Bit 11.3.5 PERIODICLISTBASE register The Periodic Frame List Base Address (PERIODLISTBASE) register contains the beginning address of the periodic frame ...
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NXP Semiconductors Bit Symbol Reset Access [1] The reserved bits should always be written with the reset value. Table 101. PERIODICLISTBASE - Periodic Frame List Base Address register bit description Address: Value read from func2 of address 10h + 34h ...
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NXP Semiconductors Table 103. ASYNCLISTADDR - Current Asynchronous List Address register bit description Address: Value read from func2 of address 10h + 38h Bit 11.3.7 CONFIGFLAG register The bit allocation of the Configure Flag ...
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NXP Semiconductors 11.3.8 PORTSC registers 1, 2 The Port Status and Control (PORTSC) register is in the auxiliary power well only reset by hardware when the auxiliary power is initially applied or in response to a Host Controller ...
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NXP Semiconductors Table 107. PORTSC Port Status and Control 1, 2 register bit description Address: Value read from func2 of address 10h + 64h + ( Bit and 14 reserved ...
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NXP Semiconductors Table 107. PORTSC Port Status and Control 1, 2 register bit description Address: Value read from func2 of address 10h + 64h + ( Bit 8 7 SAF1562_1 Product data sheet Hi-Speed ...
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NXP Semiconductors Table 107. PORTSC Port Status and Control 1, 2 register bit description Address: Value read from func2 of address 10h + 64h + ( Bit ...
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... SAF1562HL two high-speed devices connected to the SAF1562HL + V no device connected to the SAF1562HL I(VREG3V3) one high-speed device connected to the SAF1562HL two high-speed devices connected to the SAF1562HL shows the power consumption in S1 and S3 suspend modes. Power state C-bus is present ...
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NXP Semiconductors 13. Limiting values Table 110. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage to I/O pins CC(I/O) V supply voltage to internal regulator I(VREG3V3) V auxiliary supply voltage to ...
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NXP Semiconductors Table 114. Static characteristics: digital pins +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL I ...
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NXP Semiconductors Table 116. Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2 3 3 +85 C; unless otherwise specified. Abstract of the USB specification rev. ...
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NXP Semiconductors Table 119. Dynamic characteristics: high-speed source electrical characteristics +85 C; unless otherwise specified. Abstract of the USB specification rev. 2.0. DDA_AUX amb Symbol Parameter Driver characteristics ...
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NXP Semiconductors 16.1 Timing Table 122. PCI clock and IO timing Abstract of the USB specification rev. 2.0. Symbol Parameter PCI clock timing; see Figure 7 T PCICLK cycle time cyc(PCICLK) t PCICLK HIGH time HIGH(PCICLK) t PCICLK LOW time ...
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NXP Semiconductors CLK INPUT DELAY Fig 8. PCI input timing CLK OUTPUT DELAY OUTPUT Fig 9. PCI output timing t USBbit +3.3 V crossover point differential data lines the bit duration (USB data). USBbit [1] t ...
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NXP Semiconductors 17. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original ...
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NXP Semiconductors 18. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 18.1 Introduction to soldering Soldering ...
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NXP Semiconductors 18.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 12. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 125. Abbreviations Acronym CMOS DID EEPROM EHCI EMI ESD ...
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NXP Semiconductors Table 125. Abbreviations Acronym STB USB VID SAF1562_1 Product data sheet Hi-Speed Universal Serial Bus PCI Host Controller …continued Description Set-Top Box Universal Serial Bus Vendor ID Rev. 01 — 7 February 2007 SAF1562 © NXP B.V. 2007. ...
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NXP Semiconductors 20. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 [3] Open Host Controller Interface Specification for USB Rev. 1.0a [4] PCI Local Bus Specification Rev. 2.2 ...
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NXP Semiconductors 22. Legal information 22.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 24. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Table 2. Pin description . . . . . . . ...
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NXP Semiconductors Table 52. HcInterruptDisable - Host Controller Interrupt Disable register bit allocation . . . . . .41 Table 53. HcInterruptDisable - Host Controller Interrupt Disable register bit description . . . . .42 Table 54. HcHCCA - Host ...
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NXP Semiconductors Table 95. USBSTS - USB Status register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Table ...
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... NXP Semiconductors 25. Figures Fig 1. Block diagram of SAF1562HL . . . . . . . . . . . . . . . .3 Fig 2. Pin configuration for LQFP100 Fig 3. Power-on reset .10 Fig 4. Power supply connection . . . . . . . . . . . . . . . . . . .11 Fig 5. EEPROM connection diagram . . . . . . . . . . . . . . .30 Fig 6. Information loading from EEPROM . . . . . . . . . . .31 Fig 7. PCI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Fig 8. PCI input timing . . . . . . . . . . . . . . . . . . . . . . . . . .84 Fig 9. PCI output timing . . . . . . . . . . . . . . . . . . . . . . . . .84 Fig 10. USB source differential data-to-EOP transition skew and EOP width ...
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NXP Semiconductors 26. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...
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NXP Semiconductors 11.3.2 USBSTS register . . . . . . . . . . . . . . . . . . . . . . 66 11.3.3 USBINTR register . . . . . . . . . ...