SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 72
SAF1562HL/N2-T
Manufacturer Part Number
SAF1562HL/N2-T
Description
DC/DC Switching Controllers CONNECTIVITY CHIP
Manufacturer
NXP Semiconductors
Datasheet
1.SAF1562HLN2-T.pdf
(121 pages)
Specifications of SAF1562HL/N2-T
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Mounting Style
SMD/SMT
Package / Case
LQFP
Lead Free Status / RoHS Status
Compliant
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NXP Semiconductors
SAF1562
Product data sheet
11.3.4 FRINDEX register
The Frame Index (FRINDEX) register is used by the Host Controller to index into the
periodic frame list. The register updates every 125 μs—once each micro frame.
Bits N to 3 are used to select a particular entry in the periodic frame list during periodic
schedule execution. The number of bits used for the index depends on the size of the
frame list as set by the system software in FLS[1:0] (bit 3 and bit 2) of the USBCMD
register. This register must be written as a double word. Byte writes produce undefined
results. This register cannot be written unless the Host Controller is in the halted state, as
indicated by HCH (bit 12 in the USBSTS register). A write to this register while RS (bit 0 in
the USBCMD register) is set produces undefined results. Writes to this register also affect
the SOF value.
The bit allocation is given in
Table 98.
Address: Content of the base address register + 2Ch
[1]
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
FRINDEX - Frame Index register bit allocation
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2010
R/W
R/W
R/W
R/W
[1]
30
22
14
0
0
0
6
0
Table
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
98.
Hi-Speed Universal Serial Bus PCI Host Controller
R/W
R/W
R/W
R/W
FRINDEX[7:0]
28
20
12
0
0
0
4
0
reserved
reserved
FRINDEX[13:8]
R/W
R/W
R/W
R/W
[1]
[1]
27
19
11
0
0
0
3
0
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
SAF1562
© NXP B.V. 2010. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
72 of 121
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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