SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 57

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
11.1.21 HcRhStatus register
Table 81.
Address: Content of the base address register + 4Ch
This register is divided into two parts. The lower word of a double word represents the
Hub Status field, and the upper word represents the Hub Status Change field. Reserved
bits should always be written as logic 0.
Table 82.
Address: Content of the base address register + 50h
Bit
Symbol
Reset
Access
Bit
31 to 16 PPCM
15 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Symbol
[15:0]
DR
[15:0]
HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit
description
HcRhStatus - Host Controller Root Hub Status register bit allocation
CRWE
DRWE
R/W
R/W
R/W
R/W
31
23
15
7
0
0
0
0
All information provided in this document is subject to legal disclaimers.
Description
Port Power Control Mask: Each bit indicates whether a port is affected by a
global power control command when Power Switching Mode is set. When
set, only the power state of the port is affected by per-port power control
(Set/Clear Port Power). When cleared, the port is controlled by the global
power switch (Set/Clear Global Power). If the device is configured to global
switching mode (Power Switching Mode = logic 0), this field is not valid.
Bit 0 — Reserved
Bit 1 — Ganged-power mask on port 1
Bit 2 — Ganged-power mask on port 2
Device Removable: Each bit is dedicated to a port of the Root Hub. When
cleared, the attached device is removable. When set, the attached device is
not removable.
Bit 0 — Reserved
Bit 1 — Device attached to port 1
Bit 2 — Device attached to port 2
Rev. 2 — 24 November 2010
R/W
R/W
R/W
R/W
30
22
14
6
0
0
0
0
R/W
R/W
R/W
R/W
29
21
13
5
0
0
0
0
reserved
Hi-Speed Universal Serial Bus PCI Host Controller
Table 82
R/W
R/W
R/W
R/W
[1]
28
20
12
4
0
0
0
0
DR[7:0]
shows the bit allocation of the register.
reserved
reserved
R/W
R/W
R/W
R/W
27
19
11
3
0
0
0
0
[1]
[1]
R/W
R/W
R/W
R/W
26
18
10
2
0
0
0
0
SAF1562
© NXP B.V. 2010. All rights reserved.
CCIC
R/W
R/W
R/W
R/W
25
17
1
0
0
0
9
0
LPSC
57 of 121
R/W
R/W
R/W
R/W
24
16
0
0
0
0
8
0