SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 37

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAF1562
Product data sheet
Table 45.
Address: Content of the base address register + 04h
Bit
31 to 11
10
9
8
7 and 6
5
HcControl - Host Controller Control register bit description
Symbol
reserved
RWE
RWC
IR
HCFS
[1:0]
BLE
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2010
Description
-
Remote Wakeup Enable: This bit is used by the HCD to enable or disable
the remote wake-up feature on detecting upstream resume signaling.
When this bit and RD (bit 3) in the HcInterruptStatus register are set, a
remote wake-up is signaled to the host system. Setting this bit has no
impact on the generation of hardware interrupt.
Remote Wakeup Connected: This bit indicates whether the Host
Controller supports remote wake-up signaling. If remote wake-up is
supported and used by the system, it is the responsibility of the system
firmware to set this bit during POST. The Host Controller clears the bit on a
hardware reset but does not alter it on a software reset. Remote wake-up
signaling of the host system is host-bus-specific and is not described in
this specification.
Interrupt Routing: This bit determines the routing of interrupts generated
by events registered in HcInterruptStatus. If clear, all interrupts are routed
to the normal host bus interrupt mechanism. If set, interrupts are routed to
the System Management Interrupt. The HCD clears this bit on a hardware
reset, but it does not alter this bit on a software reset. The HCD uses this
bit as a tag to indicate the ownership of the Host Controller.
Host Controller Functional State for USB:
00b — USBRESET
01b — USBRESUME
10b — USBOPERATIONAL
11b — USBSUSPEND
A transition to USBOPERATIONAL from another state causes SOF
generation to begin 1 ms later. The HCD may determine whether the Host
Controller has begun sending SOFs by reading SF (bit 2) in
HcInterruptStatus.
This field may be changed by the Host Controller only when in the
USBSUSPEND state. The Host Controller may move from the
USBSUSPEND state to the USBRESUME state after detecting the
resume signaling from a downstream port.
The Host Controller enters USBSUSPEND after a software reset; it enters
USBRESET after a hardware reset. The latter also resets the Root Hub
and asserts subsequent reset signaling to downstream ports.
Bulk List Enable: This bit is set to enable the processing of the bulk list in
the next frame. If cleared by the HCD, processing of the bulk list does not
occur after the next SOF. The Host Controller checks this bit whenever it
wants to process the list. When disabled, the HCD may modify the list. If
HcBulkCurrentED is pointing to an Endpoint Descriptor (ED) to be
removed, the HCD must advance the pointer by updating
HcBulkCurrentED before re-enabling processing of the list.
Hi-Speed Universal Serial Bus PCI Host Controller
SAF1562
© NXP B.V. 2010. All rights reserved.
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