SAF1562HL/N2-T NXP Semiconductors, SAF1562HL/N2-T Datasheet - Page 115

• Manufacturer Part Number: SAF1562HL/N2-T
• Description: DC/DC Switching Controllers CONNECTIVITY CHIP
• Manufacturer: NXP Semiconductors

Specifications of SAF1562HL/N2-T

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Mounting Style: SMD/SMT
• Package / Case: LQFP
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
25. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. REVID - Revision ID register (address 08h)
Table 11. Class Code register (address 09h)
Table 12. Class Code register (address 09h)
Table 13. CLS - Cache Line Size register (address 0Ch)
Table 14. LT - Latency Timer register (address 0Dh)
Table 15. Header Type register (address 0Eh)
Table 16. Header Type register (address 0Eh)
Table 17. BAR 0 - Base Address register 0
Table 18. SVID - Subsystem Vendor ID register (address
Table 19. SID - Subsystem ID register (address 2Eh)
Table 20. CP - Capabilities Pointer register (address 34h)
Table 21. IL - Interrupt Line register (address 3Ch)
Table 22. IP - Interrupt Pin register (address 3Dh) bit
Table 23. Min_Gnt - Minimum Grant register (address 3Eh)
Table 24. Max_Lat - Maximum Latency register (address
Table 25. EHCI-specific PCI registers . . . . . . . . . . . . . . .24
Table 26. SBRN - Serial Bus Release Number register
Table 27. FLADJ - Frame Length Adjustment register
SAF1562
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
PCI configuration space registers of OHCI1,
OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .15
VID - Vendor ID register (address 00h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .16
DID - Device ID register (address 02h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .16
Command register (address 04h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Command register (address 04h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .17
Status register (address 06h) bit allocation . . .18
Status register (address 06h) bit description . .18
bit description . . . . . . . . . . . . . . . . . . . . . . . . .19
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .20
bit description . . . . . . . . . . . . . . . . . . . . . . . . .20
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .21
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
(address 10h) bit description . . . . . . . . . . . . . .22
2Ch) bit description . . . . . . . . . . . . . . . . . . . . .22
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
3Fh) bit description . . . . . . . . . . . . . . . . . . . . .24
(address 60h) bit description . . . . . . . . . . . . . .25
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 24 November 2010
Table 28. FLADJ - Frame Length Adjustment register
Table 29. PORTWAKECAP - Port Wake Capability register
Table 30. Power Management registers . . . . . . . . . . . . . 26
Table 31. Cap_ID - Capability Identifier register bit
Table 32. Next_Item_Ptr - Next Item Pointer register bit
Table 33. PMC - Power Management Capabilities register
Table 34. PMC - Power Management Capabilities register
Table 35. PMCSR - Power Management Control/Status
Table 36. PMCSR - Power Management Control/Status
Table 37. PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Table 39. PCI bus power and clock control . . . . . . . . . . 31
Table 40. Data register bit description . . . . . . . . . . . . . . 31
Table 41. USB Host Controller registers . . . . . . . . . . . . . 34
Table 42. HcRevision - Host Controller Revision register
Table 43. HcRevision - Host Controller Revision register
Table 44. HcControl - Host Controller Control register
Table 45. HcControl - Host Controller Control register
Table 46. HcCommandStatus - Host Controller Command
Table 47. HcCommandStatus - Host Controller Command
Table 48. HcInterruptStatus - Host Controller Interrupt
Table 49. HcInterruptStatus - Host Controller Interrupt
Table 50. HcInterruptEnable - Host Controller Interrupt
Table 51. HcInterruptEnable - Host Controller Interrupt
Table 52. HcInterruptDisable - Host Controller Interrupt
Table 53. HcInterruptDisable - Host Controller Interrupt
Hi-Speed Universal Serial Bus PCI Host Controller
(address 61h) bit allocation . . . . . . . . . . . . . . . 25
(address 61h) bit description . . . . . . . . . . . . . . 25
(address 62h) bit description . . . . . . . . . . . . . . 26
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 27
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 27
register bit allocation . . . . . . . . . . . . . . . . . . . . 29
register bit description . . . . . . . . . . . . . . . . . . . 29
Support Extensions register bit allocation . . . . 30
Support Extensions register bit description . . . 31
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 35
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 36
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 36
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status register bit allocation . . . . . . . . . . . . . . 39
Status register bit description . . . . . . . . . . . . . 39
Status register bit allocation . . . . . . . . . . . . . . 40
Status register bit description . . . . . . . . . . . . . 41
Enable register bit allocation . . . . . . . . . . . . . . 42
Enable register bit description . . . . . . . . . . . . . 42
Disable register bit allocation . . . . . . . . . . . . . 43
SAF1562
© NXP B.V. 2010. All rights reserved.
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