LSISAS1068 LSI, LSISAS1068 Datasheet - Page 102

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

Table 4.7
Table 4.8
4-32
31
31
31
0
0
0
0
0
PCI Memory [0] Address Map
PCI Memory [1] Address Map
0
High Priority Request MFA Queue
0
Table 4.7
Table 4.8
A bit level description of the PCI Memory and PCI I/O Spaces follows.
Register: 0x00
System Doorbell
Read/Write
The System Doorbell register is a simple message passing mechanism
that allows the system to pass single word messages to the embedded
IOP processor and vice-versa.
When a host system PCI master writes to the Host Registers->Doorbell
register, the LSISAS1068 generates a maskable interrupt to the IOP. The
value written by the host system is available for the IOP to read in the
PCI Host Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
24 23
0
Host Interrupt Status
Host Interrupt Mask
Test Base Address
0
System Doorbell
Write Sequence
Shared Memory
Request Queue
Host Diagnostic
Reply Queue
0
16 15
Reserved
Reserved
Reserved
Diagnostic Memory
0
defines the PCI Memory Space [0] address map.
defines the PCI Memory Space [1] address map.
16 15
0
0
0
System Doorbell
0
16 15
0
0
0
0
0
0
0
0
0x(Sizeof(Mem0) 1)
0
0x004C–0x007F
0x0010–0x002F
0x0038–0x003F
8
0
0x0080–
0x000C
0x0000
0x0004
0x0008
0x0030
0x0034
0x0040
0x0044
0x0048
Offset
7
0
0
0
0x(Sizeof(Mem1) 1)
0
0
0x0000–
0
0
Page
4-32
4-33
4-34
4-35
4-37
4-38
4-39
4-39
4-40
–
–
–
–
0
0
0