LSISAS1068 LSI, LSISAS1068 Datasheet - Page 146

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

IX-6
command register
configuration read command 2-11, 2-13, 2-14,
configuration space 2-9,
configuration write command 2-11, 2-13, 2-14,
DAC 2-9, 2-11,
device complexity bit
device ID configuration 3-16,
dual address cycles command 2-11,
encoding
error reporting signals
functional description
hot swap enable 3-16,
I/O read command 2-11, 2-12,
I/O space 2-9, 2-10, 4-1,
I/O space address map
I/O space and memory space
I/O write command 2-11, 2-12,
interrupt acknowledge command 2-11, 2-12,
interrupt signals
interrupts 2-16,
memory [0] address map
memory [1] address map
memory read block command 2-14,
memory read command 2-11, 2-12, 2-14, 2-15,
memory read dword command 2-12,
memory read line command 2-11, 2-15,
memory read multiple command 2-11, 2-14,
memory space 2-9, 2-10,
memory space [0] 2-4, 2-10,
memory space [1] 2-10,
memory write and invalidate command 2-11,
memory read line 2-11,
memory read multiple 2-11,
memory write 2-11,
memory write and invalidate 2-11,
memory write block 2-11,
memory write command
register
special cycle 2-11,
split completion 2-11,
4-6
address map
C_BE[3:0]/ 2-9, 2-10,
4-6
2-14
2-16
2-16
2-15,
2-16
2-11
4-14
4-38
2-15
3-6
4-2
4-3
Index
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
4-30
2-9
2-12
3-5
2-13
3-17
4-31
4-1
4-1
2-11
2-14
4-31
4-32
4-32
4-1
2-15
2-13
2-16
4-1
3-17
4-31
2-14
2-14
2-14
2-15
2-15
2-14
2-15
2-16
PCI-X
memory write block command 2-13,
memory write command 2-11, 2-15,
new capabilities bit
power management
power management interface specification
related signals
reset
special cycle command 2-11, 2-12,
split completion command
subsystem ID configuration 3-16,
system address space
133 MHz 3-16, 3-17,
133 MHz capable bit
64-bit device bit
66 MHz
alias to memory read block command
alias to memory write block command
benefits
bus commands
bus number
capability ID register
command register
commands
data parity error recovery enable bit
designed maximum cumulative read size bit
designed maximum memory read byte count
designed maximum outstanding split transac-
device complexity bit
device number bit
function number bit
maximum memory read byte count bits
maximum outstanding split transactions bits
memory read block command
memory read dword command
memory write block command
next pointer register
received split completion error message bit
split completion command
split completion discarded bit
status register
unexpected split completion bit
2-17
4-29
bit
tions bit
4-27
4-29
2-9
4-34
4-29
5-9
1-6
4-29
2-11
4-30
4-29
3-6
2-11
4-30
4-27
4-30
4-7
4-31
2-17
4-27
4-26
5-9
4-30
4-30
4-1
2-14
2-11
4-30
2-11
2-11
2-11
4-30
3-17
4-5
2-16
2-16
4-28
2-11
2-11
4-28