LSISAS1068 LSI, LSISAS1068 Datasheet - Page 31

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.1.1.3
2.1.1.4
2.1.1.5
2.1.1.6
2.1.1.7
IOP
PCI Timer and Configuration
Timer and Configuration
DMA Arbiter
External Memory
The LSISAS1068 I/O processor controls the system interface and
manages the host side of the Fusion-MPT architecture without host
processor intervention, which frees the host processor for other tasks.
The LSISAS1068 I/O processor (IOP) is a 32-bit ARM966 RISC
processor that provides instruction and data requests to streamline
operations and increase performance.
This PCI Timer and Configuration module supports the PCI configuration
register space, an industry-standard and a power-on reset (POR).
This block supports the LSISAS1068 LED and GPIO interfaces. There
are a total of 17 LED signals on the LSISAS1068. Each of the eight phys
has an LED signal to indicate activity on the link and an LED signal to
indicate an error on the link. The GPIO interface contains four
independent GPIO signals. This block provides a firmware heartbeat
LED. All LED signals (except the HB_LED/ signal) can also be configured
as GPIO signals. This block also supports internal timing adjustments
and power-on sense configuration options.
The LSISAS1068 provides the ability to transfer system memory blocks
to and from local memory through the descriptor-based DMA arbiter and
router.
The external memory controller block provides an interface for flash
ROM, NVSRAM, and PBSRAM devices. The external memory bus
provides a 32-bit memory bus, parity checking, and chip select signals
for PBSRAM, NVSRAM, and flash ROM.
Typical system configurations require a flash ROM to store firmware,
configuration information, and persistent data information.
Block Diagram Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
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