LSISAS1068 LSI, LSISAS1068 Datasheet - Page 36

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.3.1.2
2.3.1.3
2-10
PCI I/O Space
PCI Memory Space
determine if a PCI cycle intends to access the configuration register
space. The IDSEL signal behaves as a chip select signal that enables
access to the configuration register space only. The LSISAS1068 ignores
configuration read/write cycles when IDSEL is not asserted.
Bits AD[10:8] address the PCI Function Configuration Space (AD[10:8] =
0b000). The LSISAS1068 does not respond to any other encodings of
AD[10:8]. Bits AD[7:2] select one of the 64 Dword registers in the
device’s PCI Configuration Space. Bits AD[1:0] determine if the
configuration command is a Type 0 Configuration Command (AD[1:0] =
0b00) or a Type 1 Configuration Command (AD[1:0] = 0b01). Since the
LSISAS1068 is not a PCI Bridge device, all PCI Configuration
Commands designated for the LSISAS1068 must be Type 0. C_BE[3:0]/
address the individual bytes within each Dword and determine the type
of access to perform.
The PCI specification defines I/O Space as a contiguous 32-bit I/O
address that all system resources share, including the LSISAS1068. The
I/O Base Address
PCI device occupies.
The LSISAS1068 contains two PCI memory spaces: PCI Memory
Space [0] and PCI Memory Space [1]. PCI Memory Space [0] supports
normal memory accesses while PCI Memory Space [1] supports
diagnostic memory accesses. The LSISAS1068 requires 64 Kbytes of
memory space.
The PCI specification defines memory space as a contiguous 64-bit
memory address that all system resources share. The
and
PCI Memory Space [0] occupies. The
High
Space [1] occupies.
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Memory [0] High
registers determine which 64 Kbyte memory area PCI Memory
register determines the 256-byte PCI I/O area that the
registers determine which 64 Kbyte memory area
Memory [1] Low
Memory [0] Low
and
Memory [1]