LSISAS1068 LSI, LSISAS1068 Datasheet - Page 30

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.1.1
2.1.1.1
2.1.1.2
2-4
Host Interface Module Description
PCI/PCI-X Interface
System Interface
The host interface module provides an interface between the host driver
and the Quad Port modules. The host interface module controls system
DMA transfers and the host side of the LSI Logic Fusion-MPT
architecture. The host interface module contains the PCI/PCI-X interface,
system interface, PCI timer and configuration, DMA arbiter, IOP, I
TimerConfig, UART, SIO, and external memory blocks. This section
provides a detailed explanation of the host interface submodules.
The LSISAS1068 provides a PCI-X interface that supports up to a 64-bit,
133 MHz PCI-X bus. The interface is backward compatible with previous
implementations of the PCI specification, with the exception that the
LSISAS1068 does not support 5 V PCI. For more information on the PCI
interface, refer to
In combination with the IOP, the system interface supports the
Fusion-MPT architecture. The system interface efficiently passes
messages between the LSISAS1068 and the host using a high-
performance, packetized mailbox architecture. The LSISAS1068 system
interface coalesces PCI interrupts to minimize traffic on the PCI bus and
maximize system performance. The system interface contains five
hardware FIFOs for the message queuing lists: Request Free FIFO,
Request Post FIFO, Reply Free FIFO, Reply Post FIFO, and High Priority
Request FIFO. The LSISAS1068 contains control logic for the FIFOs,
while the messages are stored in the context RAM or in external
memory.
All host accesses to the IOP, external memory, and timer and
configuration subsystems pass through the system interface and use the
primary bus. The host system initiates data transactions on the primary
bus with the system interface registers. PCI Memory Space [0] and the
PCI I/O Base Address registers identify the location of the system
interface register set.
provides a bit level description of the system interface register set.
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Section 2.3, “PCI Functional
Chapter 4, “PCI Host Register
Description”.
Description”,
2
C,