LSISAS1068 LSI, LSISAS1068 Datasheet - Page 91

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

Table 4.2
PCI Configuration Space Register Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Multiple Message Enable Field Bit Encoding
request messages must align to a power of two.
provides the bit encoding of this field.
Multiple Message Capable
These read only bits indicate the number of messages
that the LSISAS1068 requests from the host. The host
system software reads this field to determine the number
of requested messages. The number of requested
messages must align to a power of two. The LSISAS1068
sets this field to 0b000 to request one message. All other
encodings of this field are reserved.
MSI Enable
System software sets this bit to enable MSI. To enable
MSI, the MSI-X bit in the
must also be cleared (‘0’). Setting this bit enables the
device to use MSI to interrupt the host and request ser-
vice. Setting this bit prohibits the LSISAS1068 from using
the INTA/ or ALT_INTA/ pins to request service from the
host. Setting this bit to mask interrupts on the INTA/ or
ALT_INTA/ pins is a violation of the PCI specification.
Bits [6:4] Encoding
0b000
0b001
0b010
0b011
0b100
0b101
0b110
0b111
Number of Allocated Messages
MSI-X Message Control
Reserved
Reserved
16
32
1
2
4
8
Table 4.2
register
[3:1]
4-21
0