LSISAS1068 LSI, LSISAS1068 Datasheet - Page 127

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

Table 5.31
1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations
Signal
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
marked RESERVED are for LSI Logic factory test use only. Refer to
Signals”
REFPLL_VDD
REFPLL_VSS
to determine how to terminate the RESERVED pads.
RXB_VDD4
RXB_VDD5
TXB_VDD3
REFCLK_B
RXB_VSS7
TXB_VDD6
TXB_VSS1
RX_VDD4
TX_VDD0
RX_VSS5
TX_VSS5
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
Listing by Pin Number
TXVDD6
RX5–
RX4+
RX4–
RX3+
RX2+
RX2–
RX7+
RX6+
RX6–
RX5+
RX3–
RX1+
RX1–
RX0+
RX0–
RX7–
TX7+
TX5+
TX4+
TX3+
TX1+
TX6+
TX2+
TX0+
TX7–
TX5–
TX3–
TX2–
TX1–
TX6–
TX4–
TX0–
Pin
VSS
VSS
VSS
VSS
VSS
N/C
Pinout
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Signal
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
SCAN_ENABLE
ISTWI_DATA
SIO_END_A
RXB_VDD1
RXB_VDD0
RXB_VDD6
RXB_VDD3
REFCLK_N
REFCLK_P
TXB_VDD5
RXB_VSS2
TXB_VDD1
TXB_VSS7
TXB_VSS4
TXB_VSS6
TXB_VSS2
TXB_VSS0
RX_VDD2
RX_VDD6
RX_VDD5
RX_VDD3
RX_VDD1
RX_VDD7
TX_VDD2
TX_VDD5
TX_VDD4
TX_VDD3
RX_VSS2
TX_VDD1
RX_VSS0
TX_VDD7
RX_VSS7
RX_VSS4
TX_VSS2
TX_VSS4
TX_VSS3
TX_VSS0
VDDIO33
VDDIO33
VDDIO33
VDDIO33
MODE[1]
MODE[3]
MODE[0]
MAD[11]
1
MAD[3]
RTRIM
FSELA
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N/C
N/C
N/C
N/C
Signal
E21
E22
E23
E24
E25
E26
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
H1
H2
H3
ACTIVE_LED[2]/
ACTIVE_LED[7]/
ACTIVE_LED[3]/
FAULT_LED[1]/
FAULT_LED[0]/
SCAN_MODE
SIO_DOUT_A
SERIAL_CLK
SIO_CLK_A
RXB_VDD2
RXB_VDD7
SIO_DIN_A
RXB_VSS5
TXB_VDD4
RXB_VSS4
TXB_VDD2
RXB_VSS1
TXB_VDD0
RXB_VSS0
TXB_VDD7
RXB_VSS6
RXB_VSS3
TXB_VSS5
TXB_VSS3
TST_RST/
RX_VDD0
UART_RX
RX_VSS6
RX_VSS3
RX_VSS1
TX_VSS7
TX_VSS6
TX_VSS1
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
MODE[4]
MODE[2]
MODE[5]
SPARE3
SPARE2
MAD[7]
MAD[0]
MAD[1]
MAD[4]
MAD[8]
Pin
VSS
VSS
VSS
VSS
N/C
N/C
Section 3.10, “JTAG and Test
Signal
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
J1
J2
J3
J4
J5
J6
J7
J8
J19
J20
J21
J22
J23
J24
J25
J26
K1
K2
K3
K4
K5
K6
K7
K8
K10
K11
K12
K13
K14
K15
K16
K17
K19
K20
K21
K22
K23
K24
ACTIVE_LED[1]/
ACTIVE_LED[0]/
ACTIVE_LED[6]/
ACTIVE_LED[5]/
ACTIVE_LED[4]/
FAULT_LED[5]/
FAULT_LED[6]/
FAULT_LED[7]/
FAULT_LED[3]/
FAULT_LED[2]/
SERIAL_DATA
NVSRAM_CS/
ISTWI_CLK
UART_TX
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
MADP[0]
MAD[10]
MAD[12]
MAD[13]
MAD[6]
MAD[5]
MAD[2]
MAD[9]
MOE1/
VDD2
VDD2
VDD2
VDD2
Pin
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
5-17