LSISAS1068 LSI, LSISAS1068 Datasheet - Page 42

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

2.3.2.18
2.3.3
2.3.4
2.3.5
2-16
PCI Arbitration
PCI Cache Mode
PCI Interrupts
Memory Write Block Command
LSISAS1068 selects the largest multiple of the cache line size based on
the transfer size. When the DMA buffer contains less data than the value
Cache Line Size
Write command on the next cache boundary to complete the data
transfer.
The LSISAS1068 uses this command to burst data to memory. The
LSISAS1068 supports this command when operating in the PCI-X bus
mode.
The LSISAS1068 contains an independent bus mastering function. The
system interface bus mastering function manages DMA operations as
well as the request and reply message frames.
The LSISAS1068 supports an 8-bit
Line Size
addresses corresponding to cache line boundaries. The LSISAS1068
determines when to issue a PCI cache command (Memory Read Line,
Memory Read Multiple, and Memory Write and Invalidate), or PCI
noncache command (Memory Read or Memory Write command).
The LSISAS1068 signals an interrupt to the host processor either using
PCI interrupt pins (INTA/ and ALT_INTA/), or Message Signaled
Interrupts (MSI and MSI-X). The Interrupt Request Routing Mode bits in
the
either the INTA/ and/or the ALT_INTA/ pin.
MSI is an optional feature that enables a device to signal an interrupt by
writing to a specified address. MSI-X is an extension of the MSI that
increases the number of available message vectors, allows software
aliasing of message vectors, and allows each message vector to use an
independent address and data value. If using MSI or MSI-X, the
LSISAS1068 does not signal interrupts on INTA/ or ALT_INTA/. Note that
enabling MSI or MSI-X to mask PCI interrupts is a violation of the PCI
Functional Description
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Host Interrupt Mask
register provides the ability to sense and react to nonaligned
register specifies, the LSISAS1068 issues a Memory
register configure the routing of each interrupt to
Cache Line Size
register. The
Cache