LSISAS1068 LSI, LSISAS1068 Datasheet - Page 125

• Manufacturer Part Number: LSISAS1068
• Manufacturer: LSI

Specifications of LSISAS1068

• Lead Free Status / RoHS Status: Not Compliant

Table 5.30
1. Pad locations marked N/C are not internally connected to the LSISAS1068 silicon. Pad locations
Signal
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
NVSRAM_CS/
PAR
PAR64
PBSRAM_CS/
PERR/
PLLVDD
PLLVSS
PROCMON
REFCLK_B
REFCLK_N
REFCLK_P
REFPLL_VDD
REFPLL_VSS
REQ/
REQ64/
RESERVED
RESERVED
RST/
RTCK_ICE
RTRIM
marked RESERVED are for LSI Logic factory test use only. Refer to
Signals”
to determine how to terminate the RESERVED pads.
Listing by Signal Name (Cont.)
AC13
AD18
AC11
AD17
AA13
AA14
AA15
AA17
AA18
AA21
AB10
AB11
AB12
AB17
AB19
AB23
AB26
AE14
AE18
AE25
AE19
AA10
AF15
AF17
AF18
AF21
Pin
AD4
AD9
M23
AD3
U21
U22
AA7
AA8
AA9
AB3
AB8
AE9
AA5
D12
C13
C14
V22
Y21
K24
B13
B14
A13
W2
W6
W3
W5
U2
N3
Y5
Y7
Y4
V4
Pinout
Copyright © 2004, 2005 by LSI Logic Corporation. All rights reserved.
Signal
RX0+
RX0–
RX1+
RX1–
RX2+
RX2–
RX3+
RX3–
RX4+
RX4–
RX5+
RX5–
RX6+
RX6–
RX7+
RX7–
RX_VDD0
RX_VDD1
RX_VDD2
RX_VDD3
RX_VDD4
RX_VDD5
RX_VDD6
RX_VDD7
RX_VSS0
RX_VSS1
RX_VSS2
RX_VSS3
RX_VSS4
RX_VSS5
RX_VSS6
RX_VSS7
RXB_VDD0
RXB_VDD1
RXB_VDD2
RXB_VDD3
RXB_VDD4
RXB_VDD5
RXB_VDD6
RXB_VDD7
RXB_VSS0
RXB_VSS1
RXB_VSS2
RXB_VSS3
RXB_VSS4
RXB_VSS5
RXB_VSS6
RXB_VSS7
SCAN_ENABLE
SCAN_MODE
SERIAL_CLK
SERIAL_DATA
SERR/
SIO_CLK_A
SIO_CLK_B
SIO_DIN_A
SIO_DIN_B
SIO_DOUT_A
Pin
D19
C18
D15
D22
D17
C23
C19
C10
G16
G10
H21
AE5
G21
G22
B24
B25
B20
B21
A19
A20
A17
B17
A10
A11
E21
B10
E12
E15
A12
E17
F18
F15
F17
F21
F19
F13
F11
F23
F22
M4
M1
C3
D9
D7
C9
G8
C7
B8
A8
B6
B7
B3
E6
E7
E9
E4
F9
F5
1
Signal
SIO_DOUT_B
SIO_END_A
SIO_END_B
SPARE2
SPARE3
STOP/
TCK
TCK_ICE
TDI
TDI_ICE
TDIODE_P
TDIODE_VSS
TDO
TDO_ICE
TMS
TMS_ICE
TN/
TRDY/
TRST/
TRST_ICE/
TST_RST/
TX0+
TX0–
TX1+
TX1–
TX2+
TX2–
TX3+
TX3–
TX4+
TX4–
TX5+
TX5–
TX6+
TX6–
TX7+
TX7–
TX_VDD0
TX_VDD1
TX_VDD2
TX_VDD3
TX_VDD4
TX_VDD5
TX_VDD6
TX_VDD7
TX_VSS0
TX_VSS1
TX_VSS2
TX_VSS3
TX_VSS4
TX_VSS5
TX_VSS6
TX_VSS7
TXB_VDD0
TXB_VDD1
TXB_VDD2
TXB_VDD3
TXB_VDD4
AC10
Pin
G20
G18
C24
AF7
N22
N23
D18
C17
D14
D10
D16
E22
B22
B23
A22
A21
B18
A18
A16
A15
A23
E19
E14
E11
F20
E18
F16
A14
F12
M6
N5
R6
R4
N2
U1
N4
D8
C4
T1
P2
P1
V1
T4
F6
A9
B9
A6
A5
B4
B5
A4
A3
E5
A7
F8
F7
L1
Section 3.10, “JTAG and Test
Signal
TXB_VDD5
TXB_VDD6
TXB_VDD7
TXB_VSS0
TXB_VSS1
TXB_VSS2
TXB_VSS3
TXB_VSS4
TXB_VSS5
TXB_VSS6
TXB_VSS7
UART_RX
UART_TX
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
VDDIO33
5-15
Pin
M11
M13
M15
M17
D11
H22
N10
N12
N14
N16
R10
R12
R14
R16
U10
U12
U14
U16
C20
C21
C26
D13
E10
E20
B19
E16
E23
K11
K13
K15
K17
P11
P13
P15
P17
A24
B11
B12
B15
B16
F14
F10
L10
L12
L14
L16
T11
T13
T15
T17
G7
C8
D4
C1
C5
C6
E8
B2