MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 157

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

DESELECT
NO OPERATION
LOAD MODE REGISTER
ACTIVE
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Notes:
Table 51: DM Operation Truth Table
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the device. Operations already in progress are not affected.
The NO OPERATION (NOP) command is used to instruct the selected device to perform
a NOP. This prevents unwanted commands from being registered during idle or wait
states. Operations already in progress are not affected.
The mode registers are loaded via inputs A[0:n]. See mode register descriptions in Stand-
ard Mode Register (page 172) and Extended Mode Register (page 176). The LOAD
MODE REGISTER command can only be issued when all banks are idle, and a subse-
quent executable command cannot be issued until
The ACTIVE command is used to activate a row in a particular bank for a subsequent
access. The values on the BA0 and BA1 inputs select the bank, and the address provided
on inputs A[0:n] selects the row. This row remains active for accesses until a PRE-
CHARGE command is issued to that bank. A PRECHARGE command must be issued
before opening a different row in the same bank.
Name (Function)
Write enable
Write inhibit
1. Used to mask write data; provided coincident with the corresponding data.
2. All states and sequences not shown are reserved and/or illegal.
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
157
DM
H
L
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
MRD is met.
Valid
DQ
X
© 2009 Micron Technology, Inc. All rights reserved.
Commands
Notes
1, 2
1, 2