MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 198

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 134: WRITE-to-READ – Uninterrupting
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
t
t
t
DQSSnom
DQSSmin
DQSSmax
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
5
5
5
1
WRITE
Bank a,
Col b
T0
Notes:
t
t
2,3
t
DQSS
DQSS
DQSS
1. The READ and WRITE commands are to the same device. However, the READ and WRITE
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. An uninterrupted burst of 4 is shown.
4.
5. D
D
b
IN
commands may be to different devices, in which case
READ command could be applied earlier.
t
WTR is referenced from the first positive CK edge after the last data-in pair.
NOP
D
IN
T1
b
IN
b = data-in for column b; D
b+1
D
D
b
IN
IN
T1n
b+1
D
IN
b+2
b+1
D
D
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
IN
IN
b+2
NOP
D
T2
IN
b+3
b+2
D
D
IN
IN
b+3
D
T2n
IN
198
b+3
D
IN
NOP
T3
OUT
t
WTR
n = data-out for column n.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
4
Bank a,
READ
Col n
T4
Don’t Care
t
WTR is not required and the
CL = 2
CL = 2
CL = 2
T5
NOP
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
OUT
OUT
n
n
n
T6
NOP
D
n + 1
D
n + 1
D
n + 1
OUT
OUT
OUT
T6n