MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 29

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Asynchronous Interface Bus Operation
Table 10: Asynchronous Interface Mode Selection
Asynchronous Enable/Standby
Asynchronous Commands
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Mode
Standby
Command input
Address input
Data input
Data output
Write protect
1
2
Notes:
The bus on the device is multiplexed. Data I/O, addresses, and commands all share the
same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and com-
mands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, address input
cycles, and one or more data cycles, either READ or WRITE.
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power con-
sumption.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn-
chronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
An asynchronous command is written from I/O[7:0] to the command register on the
rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are
accepted by die (LUNs) even when they are busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a command
is issued.
1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = V
2. WP# should be biased to CMOS LOW or HIGH for standby.
CE#
H
or V
X
L
L
L
L
IL
.
CLE
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
X
H
X
L
L
L
ALE
29
X
H
X
L
L
L
Asynchronous Interface Bus Operation
Micron Technology, Inc. reserves the right to change products or specifications without notice.
WE#
H
X
X
RE#
H
H
H
X
X
© 2009 Micron Technology, Inc. All rights reserved.
I/Ox
X
X
X
X
X
X
0V/V
WP#
H
H
H
X
L
CC
IH