MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 203

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 139: WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
DQS
DQS
DQS
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DM
DM
DM
DQ
DQ
DQ
CK#
5, 6
5, 6
5, 6
CK
1
7
6
7
6
7
6
WRITE
Bank a,
Col b
T0
Notes:
2
t
t
t
DQSS
DQSS
DQSS
1. An interrupted burst of 8 is shown; one data element is written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4.
5. DQS is required at T4 and T4n to register DM.
6. If a burst of 4 is used, DQS and DM are not required at T3, T3n, T4, and T4n.
7. D
D
b
IN
t
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
IN
D
T1
b
IN
b = data-in for column b.
D
b
IN
T1n
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
NOP
T2
T2n
203
T3
NOP
t
WR
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3n
4
NOP
T4
Don’t Care
T4n
(a or all)
T5
PRE
Bank
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3
WRITE Operation
Transitioning Data
T6
NOP