MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 201

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 137: WRITE-to-PRECHARGE – Uninterrupting
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DQ
DQ
DQ
DM
DM
DM
CK
1
6
6
6
WRITE
Bank a,
Col b
T0
Notes:
2,4
t
DQSS
t
DQSS
t
DQSS
1. An uninterrupted burst 4 of is shown.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. PRE = PRECHARGE.
4. The PRECHARGE and WRITE commands are to the same device. However, the PRE-
5.
6. D
D
b
IN
CHARGE and WRITE commands can be to different devices; in this case,
required and the PRECHARGE command can be applied earlier.
t
WR is referenced from the first positive CK edge after the last data-in pair.
NOP
D
IN
T1
b
IN
b = data-in for column b.
b+1
D
D
b
IN
IN
T1n
b+1
D
IN
b+2
b+1
D
D
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
IN
IN
b+2
NOP
D
T2
IN
b+3
D
b+2
D
IN
IN
b+3
T2n
D
IN
201
b+3
D
IN
T3
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
NOP
WR
T4
5
Don’t Care
(a or all)
PRE
T5
Bank
© 2009 Micron Technology, Inc. All rights reserved.
3,4
WRITE Operation
Transitioning Data
t
WR is not
T6
NOP