MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 194

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 129: Write – DM Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
BA0, BA1
Address
DQS
DQ
CK#
CKE
A10
DM
CK
6
t
t
IS
IS
NOP
T0
t
1
t
IH
IH
Notes:
t
t
ACTIVE
Bank x
IS
IS
Row
Row
T1
t
t
IH
IH
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T8 is “Don’t Care” if A10 is HIGH at T8.
6. D
t
CK
these times.
t
IN
t
RCD
RAS
n = data-in from column n.
NOP
T2
1
t
CH
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
CL
t
WPRES
t
WRITE
IS
Bank x
Note 4
Col n
T3
t
IH
t
2
DQSS (NOM)
194
t
DS
NOP
T4
D
n
IN
t
WPRE
1
t
DH
T4n
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
DQSL
NOP
n+2
T5
D
IN
t
DQSH
1
T5n
t
WPST
NOP
T6
1
Don’t Care
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation
t
NOP
WR
T7
1
1
Transitioning Data
One bank
All banks
Bank x
PRE
T8
3
5
t
RP