MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 81

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

ERASE BLOCK TWO-PLANE (60h-D1h)
Figure 50: ERASE BLOCK TWO-PLANE (60h–D1h) Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
The ERASE BLOCK TWO-PLANE (60h-D1h) command queues a block in the specified
plane to be erased in the NAND Flash array. This command can be issued one or more
times. Each time a new plane address is specified, that plane is also queued for a block
to be erased. To specify the final block to be erased and to begin the ERASE operation
for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This
command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To queue a block to be erased, write 60h to the command register, then write three ad-
dress cycles containing the row address; the page address is ignored. Conclude by
writing D1h to the command register. The selected die (LUN) will go busy (RDY = 0,
ARDY = 0) for
To determine the progress of
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK TWO-PLANE (60h-
D1h) commands can be issued to queue additional planes for erase. Alternatively, the
ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks.
For two-plane addressing requirements for the ERASE BLOCK TWO-PLANE (60h-D1h)
and ERASE BLOCK (60h-D0h) commands, see Two-Plane Operations.
Cycle type
I/O[7:0]
RDY
Command
t
DBSY.
60h
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Address
R1
81
t
DBSY, the host can monitor the target's R/B# signal, or
Address
R2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Address
R3
Command
D1h
t WB
t DBSY
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Erase Operations
Command
60h
Address
...