MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 84

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 53: INTERNAL DATA MOVE (85h-10h) with Internal ECC Enabled
Figure 54: INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT with Internal ECC Enabled
PROGRAM FOR INTERNAL DATA MOVE (85h–10h)
Figure 55: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
I/O[7:0]
I/O[7:0]
R/B#
R/B#
Cycle type
00h
00h
I/O[7:0]
Source address
Source address
RDY
(5 cycles)
Address
(5 cycles)
Address
Command
35h
35h
The PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is functionally iden-
tical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to
the command register, cache register contents are not cleared.
85h
t
R_ECC
t
R_ECC
Address
SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
70h
C1
70h
Status
Address
Status
C2
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
00h
00h
Address
R1
D
D
OUT
OUT
Address
84
D
is optional
R2
D
OUT
OUT
is optional
85h
Address
Destination address
R3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
(5 cycles)
85h
Address
Destination address
Command
(5 cycles)
Address
Internal Data Move Operations
10h
Data
(Unlimitted repetitions are possible)
t WB
85h
Column address 1, 2
10h
(2 cycles)
Address
t
PROG_ECC
t PROG
Data
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SR bit 0 = 0 READ successful
SR bit 1 = 0 READ error
70h
10h
t
PROG_ECC
Status
00h
70h