MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 206

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MT29C4G48MAZAPAKD-5 IT

Manufacturer Part Number
MT29C4G48MAZAPAKD-5 IT
Description
MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
Manufacturer
Micron Technology Inc
Figure 140: Bank Read – With Auto Precharge
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Case 1:
Case 2:
Command
BA0, BA1
Address
DQ
DQ
DQS
DQS
t
t
CK#
CKE
A10
AC (MIN) and
AC (MAX) and
DM
CK
4,5
4,5
4
4
t
t
IS
IS
NOP
T0
t
DQSCK (MIN)
t
t
DQSCK (MAX)
1
t
IH
IH
Notes:
ACTIVE
Bank x
t
t
IS
IS
Row
Row
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4 in the case shown.
3. Enable auto precharge.
4. Refer to Figure 125 (page 189) and Figure 126 (page 190) for detailed DQS and DQ timing.
5. D
t
t
IH
IH
t
CK
these times.
OUT
t
t
RAS
RCD
t
RC
n = data-out from column n.
NOP
T2
1
t
CH
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
CL
t
t
Note 3
Bank x
READ
IS
LZ (MIN)
Col n
T3
t
2
IH
206
t
CL = 2
RPRE
t
t
LZ (MIN)
AC (MIN)
NOP
T4
1
t
AC (MAX)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
D
RPRE
OUT
n
t
DQSCK (MIN)
NOP
D
n + 1
T5
D
OUT
OUT
t
n
DQSCK (MAX)
1
T5n
D
D
OUT
n + 1
x
OUT
t
RP
NOP
D
x + 1
T6
t
OUT
D
RPST
OUT
x
Don’t Care
1
t
HZ (MAX)
© 2009 Micron Technology, Inc. All rights reserved.
T6n
D
x + 1
t
RPST
OUT
Auto Precharge
NOP
T7
1
Transitioning Data
ACTIVE
Bank x
Row
Row
T8

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