MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 188

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 124: READ-to-PRECHARGE
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Command
Address
Address
DQS
DQS
CK#
DQ
CK#
DQ
CK
CK
4
4
Notes:
Banka,
Col n
Banka,
Col n
READ
READ
T0
T0
1. BL = 4, or an interrupted burst of 8 or 16.
2. PRE = PRECHARGE command.
3. ACT = ACTIVE command.
4. D
5. Shown with nominal
6. READ-to-PRECHARGE equals 2 clocks, which enables 2 data pairs of data-out.
7. A READ command with auto precharge enabled, provided
1
1
cause a precharge to be performed at x number of clock cycles after the READ com-
mand, where x = BL/2.
OUT
n = data-out from column n.
CL = 2
NOP
NOP
T1
T1
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
CL = 3
T1n
T1n
(a or all)
t
(a or all)
D
Bank a,
Bank a,
AC,
OUT
n
T2
T2
PRE
PRE
188
t
2
2
DQSCK, and
D
n + 1
T2n
T2n
OUT
D
OUT
n
D
n + 2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T3
NOP
T3
NOP
OUT
t
DQSQ.
D
n + 1
Don’t Care
OUT
t
T3n
t
T3n
D
n + 3
RP
RP
OUT
D
n + 2
OUT
T4
NOP
T4
NOP
D
n + 3
OUT
t
RAS (MIN) is met, would
Transitioning Data
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READ Operation
Bank a,
Bank a,
T5
T5
ACT
Row
ACT
Row
3
3