MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 24

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Architecture
Figure 9: NAND Flash Die (LUN) Functional Block Diagram
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
LOCK
WE#
WP#
R/B#
I/Ox
ALE
CE#
RE#
CLE
1
Note:
Control
control
logic
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row
decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word
by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput. The status register reports
the status of die operations.
I/O
1. The LOCK pin is used on the 1.8V device.
Command register
Address register
Status register
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Column decode
Cache register
NAND Flash
Data register
(2 planes)
array
© 2009 Micron Technology, Inc. All rights reserved.
ECC
V
CC
Architecture
V
SS