EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 15
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Electrical Characteristics
Table 1–9. Bus Hold Parameters (Part 2 of 2)
Table 1–10. OCT Calibration Accuracy Specifications for Stratix IV Devices
April 2011 Altera Corporation
Parameter Symbol
Low
overdrive
current
High
overdrive
current
Bus-hold
trip point
25-Ω R
3.0, 2.5, 1.8, 1.5, 1.2
50-Ω R
3.0, 2.5, 1.8, 1.5, 1.2
50-Ω R
2.5, 1.8, 1.5, 1.2
20-Ω, 40-Ω, and
60-Ω R
3.0, 2.5, 1.8, 1.5, 1.2
25-Ω R
3.0, 2.5, 1.8, 1.5, 1.2
Notes to
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25-
(3) 20-
Symbol
Ω
Ω
S
S
T
S
S_left_shift
Table
(3)
R
R
(2)
S
S
is not supported for 1.5 V and 1.2 V in Row I/O.
is not supported for 1.5 V and 1.2 V in Row I/O.
1–10:
V
I
I
ODH
ODL
TRIP
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block.
termination calibration accuracy specifications.
Internal series termination
with calibration (25-Ω
setting)
Internal series termination
with calibration (50-Ω
setting)
Internal parallel termination
with calibration (50-Ω
setting)
Expanded range for internal
series termination with
calibration (20-Ω, 40-Ω , and
60-Ω R
Internal left shift series
termination with calibration
(25-Ω R
Conditions
0V < V
0V < V
V
V
—
CCIO
CCIO
S
S_left_shift
IN
IN
Description
setting)
<
<
setting)
0.45
Min
—
—
1.2 V
-120
Max
0.95
120
V
V
V
V
V
CCIO
CCIO
CCIO
CCIO
CCIO
0.50
Min
—
—
Conditions
1.5, 1.2 V
1.5, 1.2 V
1.5, 1.2 V
1.5, 1.2 V
1.5 V
= 3.0, 2.5, 1.8,
= 3.0, 2.5, 1.8,
= 2.5, 1.8, 1.5,
= 3.0, 2.5, 1.8,
= 3.0, 2.5, 1.8,
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
1.2 V
-160
Max
1.00
160
Table 1–10
0.68
Min
—
—
1.8 V
V
(Note 1)
CCIO
± 10
± 10
± 10
lists the Stratix IV OCT
Max
-200
1.07
± 8
± 8
C2
200
Calibration Accuracy
0.70
Min
—
—
C3,I3
2.5 V
± 10
± 10
± 10
± 8
± 8
-300
Max
1.70
300
C4,I4
± 10
± 10
± 10
0.80
± 8
± 8
Min
—
—
3.0 V
-500
2.00
Max
500
Unit
%
%
%
%
%
1–7
Unit
µA
µA
V