EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 57

IC STRATIX IV FPGA 530K 1152HBGA

EP4SGX530HH35C2N

Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP4SGX530HH35C2N
Manufacturer:
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Quantity:
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Part Number:
EP4SGX530HH35C2N
Manufacturer:
ALTERA
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Part Number:
EP4SGX530HH35C2NAD
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Part Number:
EP4SGX530HH35C2NAE
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices—Preliminary
of 3)
April 2011 Altera Corporation
M144K
Block
Notes to
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50%
(2) This is only applicable to the Stratix IV E and GX devices.
(3) When you use the error detection CRC feature, there is no degradation in F
Memory
(3)
output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
Table
Single-port
2K×72
Simple dual-port
2K×72
Simple dual-port
2K×72, with the
read-during-write
option set to Old
Data
Simple dual-port
2K×64 (with ECC)
True dual-port
4K×36
True dual-port
4K×36, with the
read-during-write
option set to Old
Data
ROM 1 Port
ROM 2 Port
Min Pulse Width
(clock high time)
Min Pulse Width
(clock low time)
1–36:
1
Mode
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
ALUTs
Resources Used
0
0
0
0
0
0
0
0
TriMatrix
Memory
1
1
1
1
1
1
1
1
Commercial/
Speed Grade
Industrial
–2 /–2×
475
465
260
335
400
245
540
500
700
500
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
MAX
Commercial/
Speed Grade
Industrial
.
440
435
240
300
375
230
500
465
755
625
–3
Commercial/
Speed Grade
Industrial
Performance
380
385
205
255
330
205
435
400
860
690
–4
–3 Industrial
Speed Grade
400
375
225
295
350
225
450
425
860
690
(2)
(Note 1)
–4 Industrial
Speed Grade
(Part 3
350
325
200
250
310
200
420
400
950
690
(2)
1–49
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps

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