EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 68

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–60
Table 1–48. Memory Output Clock Jitter Specification for Stratix IV Devices
Table 1–49. OCT Calibration Block Specifications for Stratix IV Devices
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Clock period jitter
Cycle-to-cycle period jitter
Duty cycle jitter
Notes to
(1) The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
(2) The clock jitter specification applies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL
(3) The memory output clock jitter stated in
OCTUSRCLK
T
T
T
OCTCAL
OCTSHIFT
RS_RT
output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible.
Symbol
Table
Parameter
1–48:
1
1
Number of OCTUSRCLK clock cycles required for OCT R
calibration
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT R
Clock required by OCT calibration blocks
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
Table 1–48
For the Stratix IV GT –1 and –2 speed grade specifications, refer to the –2/–2× speed
grade column. For the Stratix IV GT –3 speed grade specification, refer to the –3 speed
grade column.
OCT Calibration Block Specifications
Table 1–49
Regional
Regional
Regional
Network
Global
Global
Global
Clock
S
and R
lists the memory output clock jitter specifications for Stratix IV devices.
lists the OCT calibration block specifications for Stratix IV devices.
Table 1–48
T
Description
Symbol
t
t
t
t
t
JIT(duty)
t
JIT(duty)
JIT(per)
JIT(per)
JIT(cc)
JIT(cc)
is applicable when an input jitter of 30 ps is applied.
-100
-150
Min
-50
-50
-75
-75
Speed Grade
–2/–2X
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Max
100
150
50
50
75
75
S
/R
-82.5
-82.5
-110
-165
Min
-55
-90
T
Speed Grade
(Note
–3
Min
—
—
—
—
1), (2),
82.5
82.5
Max
110
165
55
90
1000
(3)
Typ
2.5
—
28
-82.5
-82.5
-110
-165
April 2011 Altera Corporation
Min
-55
-90
Speed Grade
Switching Characteristics
–4
Max
20
—
—
—
Max
82.5
82.5
110
165
55
90
Cycles
Cycles
MHz
Unit
ns
Unit
ps
ps
ps
ps
ps
ps