EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 62

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–54
Table 1–41. High-Speed I/O Specifications
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Transmitter
True Differential I/O
Standards - f
(data rate)
Emulated
Differential I/O
Standards with
Three External
Output Resistor
Networks - f
(data rate)
Emulated
Differential I/O
Standards with One
External Output
Resistor - f
(data rate)
t
Differential I/O
Standards
t
Differential I/O
Standards with
Three External
Output Resistor
Network
t
Differential I/O
Standards with One
External Output
Resistor Network
t
t
DUTY
RISE &
x Jitter
x Jitter
x Jitter
Symbol
- True
- Emulated
- Emulated
t
FALL
HSDR
(5)
HSDR
HSDR
SERDES factor J = 3 to 10
True Differential I/O Standards
Standards with Three External
Tx output clock duty cycle for
Standards with One External
SERDES factor J = 4 to 10
Output Resistor Networks
Differential I/O Standards
Total Jitter for Data Rate,
Total Jitter for Data Rate,
Total Jitter for Data Rate,
Emulated Differential I/O
Emulated Differential I/O
Total Jitter for Data Rate
600 Mbps to 1.25 Gbps
both True and Emulated
600 Mbps to 1.6 Gbps
Uses an SDR Register
SERDES factor J = 2,
SERDES factor J = 1,
Uses DDR Registers
Output Resistor
< 600 Mbps
< 600 Mbps
Conditions
—
(Note 1), (2), (10)
(8)
–2/–2× Speed Grade
Min
—
—
—
—
—
45
—
—
—
(4)
(4)
(4)
(4)
(4)
Typ
—
—
—
—
—
—
—
—
—
—
50
—
—
—
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
(Part 2 of 3)—Preliminary
0.125
1600
1250
Max
311
160
300
160
250
460
0.1
0.2
55
(4)
(4)
Min
(4)
(4)
(4)
(4)
(4)
—
—
—
—
—
45
—
—
—
–3
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
50
—
—
—
1250
1152
0.15
Max
200
160
300
200
250
500
0.1
0.2
(4)
(4)
55
April 2011 Altera Corporation
Min
—
—
—
—
—
45
—
—
—
(4)
(4)
(4)
(4)
(4)
Switching Characteristics
–4
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
50
—
—
—
1250
Max
0.25
0.15
800
200
160
325
200
300
500
0.1
55
(4)
(4)
Mbps
Mbps
Mbps
Mbps
Mbps
Unit
ps
UI
ps
UI
UI
ps
ps
ps
%