EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 70

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–62
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Programmable Output Buffer Delay
Table 1–52
of the output buffer. The default delay is 0 ps.
Table 1–52. Programmable Output Buffer Delay
D
Note to
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
OUTBUF
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
Table
Symbol
lists the delay chain settings that control the rising and falling edge delays
1–52:
Rising and/or falling edge
delay
Parameter
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
(Note 1)
0 (default)
Typical
100
150
50
April 2011 Altera Corporation
Unit
ps
ps
ps
ps
I/O Timing