EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 23
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–23. Transceiver Specifications for Stratix IV GX Devices (Part 2 of 9)
April 2011 Altera Corporation
Peak-to-peak
differential input voltage
Spread-spectrum
modulating clock
frequency
Spread-spectrum
downspread
On-chip termination
resistors
V
V
Transmitter REFCLK
Phase Noise
Transmitter REFCLK
Phase Jitter (rms) for
100 MHz REFCLK
R
Transceiver Clocks
Calibration block clock
frequency
fixedclk clock
frequency
reconfig_clk clock
frequency
Delta time between
reconfig_clks
Transceiver block
minimum power-down
(gxb_powerdown)
pulse width
ICM
ICM
REF
(AC coupled)
(DC coupled)
Description
Symbol/
(2)
(19)
10 KHz to 20 MHz
standard for PCIe
clock frequency
reference clock
reconfiguration
PCIe Receiver
Conditions
HCSL I/O
100 KHz
≥ 1 MHz
Dynamic
100 Hz
10 KHz
Detect
10 Hz
1 KHz
PCIe
PCIe
—
—
—
—
—
—
—
37.5
Min
200
250
2.5/
30
—
—
—
—
—
—
—
—
—
—
10
—
—
(4)
1
–2 Commercial
Speed Grade
1100 ± 10%
-0.5%
± 1%
2000
0 to
100
125
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
1600
-110
-120
-120
-130
Max
550
-50
-80
125
33
—
—
—
—
50
—
3
2
37.5
Min
200
250
2.5/
Commercial/Industrial
30
—
—
—
—
—
—
—
—
—
—
10
—
—
(4)
1
Speed Grade
–2× Commercial
1100 ± 10%
-0.5%
± 1%
2000
0 to
100
125
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
and
–3
(1)
1600
-110
-120
-120
-130
Max
550
125
-50
-80
33
—
—
—
—
50
—
3
2
Commercial/Industrial
37.5
Min
2.5/
200
250
30
—
—
—
—
—
—
—
—
—
—
10
—
—
(4)
1
Speed Grade
1100 ± 10%
-0.5%
± 1%
2000
0 to
100
125
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–4
1–15
1600
-110
-120
-120
-130
Max
550
125
-50
-80
33
—
—
—
—
50
—
3
2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
MHz
Unit
mV
kHz
mV
mV
ms
—
—
ps
µs
Ω
Ω