EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 55
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EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–35. Block Performance Specifications for Stratix IV DSP Devices
Table 1–36. TriMatrix Memory Block Performance Specifications for Stratix IV Devices—Preliminary
of 3)
April 2011 Altera Corporation
9×9-bit multiplier
12×12-bit multiplier
18×18-bit multiplier
36×36-bit multiplier
18×18-bit multiply accumulator
18×18-bit multiply adder
18×18-bit multiply adder-signed full precision
18×18-bit multiply adder with loopback
36-bit shift (32-bit data)
Double mode
Notes to
(1) Maximum is for fully pipelined block with Round and Saturation disabled.
(2) Maximum for loopback input registers disabled, Round and Saturation disabled, and pipeline and output registers enabled.
MLAB
Memory
(3)
Table
Single port 64×10
Simple dual-port
32×20
Simple dual-port
64×10
ROM 64×10
ROM 32×20
1–35:
Mode
Mode
DSP Block Specifications
Table 1–35
TriMatrix Memory Block Specifications
Table 1–36
ALUTs
Resources Used
0
0
0
0
0
lists the Stratix IV DSP block performance specifications.
lists the Stratix IV TriMatrix memory block specifications.
TriMatrix
(2)
Memory
1
1
1
1
1
Commercial/
Speed Grade
Multipliers
Industrial
Resources
Number of
–2 /–2×
Used
600
600
600
600
600
1
1
1
1
4
4
2
2
1
1
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
Commercial/
Speed Grade
Industrial
–2/–2×
Speed
Grade
500
500
500
500
500
520
540
600
480
490
510
490
390
490
480
–3
(Note
Performance
Commercial/
Speed Grade
1)—Preliminary
Industrial
Speed
Grade
Performance
460
500
550
440
440
470
450
350
440
440
450
450
450
450
450
–3
–4
–3 Industrial
Speed Grade
Speed
Grade
400
440
480
380
380
410
390
310
380
380
–4
500
500
500
500
500
(2)
(Note 1)
–4 Industrial
Speed Grade
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
(Part 1
450
450
450
450
450
(2)
1–47
MHz
MHz
MHz
MHz
MHz
Unit