EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 64
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EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
1–56
Table 1–42. DPA Lock Time Specifications—Stratix IV ES Devices Only
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
SPI-4
Parallel Rapid I/O
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time applies to both commercial and industrial grade.
(4) This is the number of repetition for the stated training pattern to achieve 256 data transitions.
(5) Slow clock = Data rate (Mbps)/Deserialization factor.
Standard
Table 1–42
:
00000000001111111111
Table 1–42
Figure 1–4
Figure 1–4. DPA Lock Time Specification with DPA PLL Calibration Enabled
Training Pattern
rx_dpa_locked
00001111
10010000
10101010
01010101
rx_reset
lists the DPA lock time specifications for Stratix IV ES devices.
shows the DPA lock time specifications with DPA PLL calibration enabled.
Number of Data
one repetition
Transitions in
of training
pattern
transitions
256 data
2
2
4
8
8
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
clock cycles
96 slow
repetitions
transitions
Number of
per 256
data
128
128
64
32
32
(4)
(Note
DPA Lock Time
transitions
256 data
1), (2),
without DPA PLL
without DPA PLL
without DPA PLL
without DPA PLL
without DPA PLL
with DPA PLL
with DPA PLL
with DPA PLL
with DPA PLL
with DPA PLL
Condition
calibration
calibration
calibration
calibration
calibration
calibration
calibration
calibration
calibration
calibration
clock cycles
(3)
96 slow
April 2011 Altera Corporation
transitions
2x96 slow clock cycles
2x96 slow clock cycles
2x96 slow clock cycles
2x96 slow clock cycles
2x96 slow clock cycles
256 data
3x256 data transitions +
3x256 data transitions +
3x256 data transitions +
3x256 data transitions +
3x256 data transitions +
Switching Characteristics
256 data transitions
256 data transitions
256 data transitions
256 data transitions
256 data transitions
Maximum
(5)
(5)
(5)
(5)
(5)