PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 104

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
10.3.2 Simple Peripheral Capabilities (‘XIO-8/16’)
PNX15xx/952x Series as PCI master allows TM3260 to generate all single cycle PCI
transaction types, including memory cycles, I/O cycles, configuration cycles and
interrupt acknowledge cycles. As PCI target, PNX15xx/952x Series responds to
memory transactions and configuration type cycles, but not to I/O cycles.
PNX15xx/952x Series can act as PCI bus arbiter for up to 3 external masters, i.e.
total of 4 masters with PNX15xx/952x Series, without external logic.
PCI clock is an input to PNX15xx/952x Series, but if desired the general purpose
PNX15xx/952x Series PCI_SYS_CLK clock output can be used as the PCI 33 MHz
clock for the entire system.
Table 8
Table 8: PNX15xx/952x Series PCI capabilities
The 16-bit micro-processor peripheral interface is a master-only interface, and
provides non-multiplexed address and data lines. A total of 26 address bits are
provided, as well as a bi-directional, 16-bit data bus. Five device profiles are provided,
each generating a chip-select for external devices. Up to 64 MB of address space is
allowed per device profile. The interface control signals are compatible with a
Motorola 68360 bus interface, and support both fixed wait-state or dynamic
completion acknowledgment.
A total of 5 pre-decoded Chip Select pins are available to accommodate typical
outside slave configurations with minimal or no external glue logic. Each chip select
pin has an associated programmable address range within the XIO address space.
Each chip select pin can also choose to obey external DTACK completion signalling,
or be set to have a pre-programmed number of wait cycles.
The peripheral interface derives 24 of the 26 address wires and 8 out of the 16 data
wires from the PCI AD[31:0] pins. The remaining pins are XIO specific and non PCI
shared. An ‘XIO’ access looks like a valid PCI transaction to PCI master/targets on
the same wires. Unused XIO pins are available as GPIO pins.
As PCI Target it responds to
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
summarizes the PCI features supported by the PNX15xx/952x Series.
Rev. 4.0 — 03 December 2007
As PCI master it initiates
IO Read
IO Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
Interrupt Acknowledge
PNX15xx/952x Series
Chapter 2: Overview
© NXP B.V. 2007. All rights reserved.
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