PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 410

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
Table 20: QVCP 1 Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
31:6
5
4
3
2
1
0
Offset 0x10 E240
31:10
9
8:1
0
Offset 0x10 E244
31:24
23:16
15:8
Symbol
Unused
Buffer toggle
Layer_Start_Field
Premult
Alpha_use
422:444_Interspersed
422:444_Enable
Unused
Layer upload
Unused
LayerN_Enable
Alpha
Red
Green
Layer Status/Control
LUT Programming
…Continued
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
-
0
1
0
0
0
0
-
-
-
0
0
0
0
Value
Rev. 4.0 — 03 December 2007
Description
This bit controls the DMA buffer mode:
Field in which the layer gets actually enabled once the
LayerN_Enable bit is set. This bit is used to invert the internal odd/
even signal. If the result of the operation Layer_Start_Field xor OE
is true the layer is enabled, otherwise the layer stays disabled until
the OE signal changes.
In non-interlaced modes:
this bit must be set to 1’b1 since the internal odd/even signal is
forced to zero.
In interlaced modes:
LayerNStartY (0x10,E230) >= 0, set this bit to 0
LayerNStartY (0x10,E230) < 0, set this bit to 1
If this bit is set, the incoming pixels are premultiplied with alpha.
That disables the new x alpha multiplication in the mixer stage if
alpha blending is enabled.
Controls which alpha value is used for blending in the layer mixer
stage
Chroma upsample filter operation mode
Chroma upsample filter enable
This bit indicates if the register upload into the shadow area is still in
progress.
This register reads always 0 if the screen timing generator is not
enabled
Alpha value for LUT programming
Red value for LUT programming
Green value for LUT programming
1 = Always toggle between buffer A and B (A=odd field, B=even
field).
0 = No buffer toggle, always fetch from buffer spec A.
1 = Use previous alpha
0 = Use alpha of current layer
1 = use this mode if input samples are arranged interspersed
0 = use this mode if input samples are arranged co-sited
1 = chroma upsample filter is enabled
0 = chroma upsample filter is in bypass mode
1 = New register upload possible, previous upload is complete
0 = Upload in progress, DO NOT reprogram any registers as the
results are undetermined
0 = Disable layer N
1 = Enable layer N
PNX15xx/952x Series
Chapter 11: QVCP
© NXP B.V. 2007. All rights reserved.
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