PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 816

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 7:
AD31
msb
P2.g P2.B
P2.g P2.B
P1.R
P1.R
A+3
A+3
Big-Endian External CPU Drawing Two RGB-565 Pixels
A
A
P1.G
P1.G
P2.R P1.g
P2.R P1.g
A+2
A+1
A+1
A+2
P1.B
P1.B
Note that the Power Macintosh architecture contains a PCI bridge that maintains byte
address invariance. Since all stages inside the PNX15xx/952x Series maintain byte
addresses, the end-to-end result of the complex sequence of actions is a successfully
rendered pair of RGB565 pixels.
It is recommended to use only external big-endian CPU/PCI bridge combinations that
implement the Power Macintosh style byte-invariant address model with the
PNX15xx/952x Series. Some external CPU PCI bridges may only contain a static,
transaction-size CPU unaware swapper. The use of such external components is not
recommended and will require special care in software.
P1.g P1.B
P1.g P1.B
P1.g P1.B
P2.R
P2.R
P1.R
A+2
A+1
A+2
A+1
A+1
A
P2.G
P2.G
P1.G
P1.R P1.g
P1.R P1.g
P1.R P1.g
Rev. 4.0 — 03 December 2007
A+3
A+3
A+1
A
A
A
P2.B
P2.B
P1.B
lsb
AD00
Data byte address association
PowerPC CPU data byte address association
‘swap’ as performed by Power Mac PCI bridge
(for 32-bit CPU store operations)
‘GIB Endian’ RGB565 transport across PCI bus, as described in
PCI Multimedia Design Guide, Revision 1.0
“g”represents partial bits from the “G” pixel
Big-Endian View of resulting SDRAM content
Data byte address association
PowerPC CPU Register content create by software
32 lsbits (or msbits) of 64-bit QVCP read across MTL Bus
Data byte address association
Data byte address association
QVCP view after unit unpack
QVCP view after big-endian mode swap
PNX15xx/952x Series
Chapter 29: Endian Mode
© NXP B.V. 2007. All rights reserved.
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