PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 671

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
2. Functional Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.1 Chip I/O and System Interconnections
Figure 1
On the left-hand side, the LAN100 is connected to the off-chip Ethernet PHY using
the Media Independent Interface (MII) or Reduced Media Independent Interface
(RMII), which includes transmit, receive, and management connections. On the
right-hand side, the LAN100 is connected to the on-chip system buses:
Figure 1:
•
•
(R)MII Tx
(R)MII Rx
The MMIO control port of the LAN100 allows CPU access to the LAN100’s
internal registers via the internal DCS bus of the PNX15xx/952x Series. The
LAN100 MMIO port is a slave on the DCS bus.
The Direct Memory Access (DMA) port of the LAN100 performs DMA via the
internal MTL bus of the PNX15xx/952x Series. The LAN100 can initiate
transactions while it is a master on the MTL bus. The LAN100 has multiple DMA
interfaces to allow both non-real-time and real-time transmit modes, and receive
mode.
PHY
MIIM
presents a simplified view of the I/O interfaces and system interconnection.
Simplified LAN100 I/O Block Diagram
LAN100
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
Non-real-time transmit
Real-time transmit
Descriptors
Descriptors
Descriptors
Descriptors
Descriptors
Descriptors
Receive
Status
Status
Status
Status
Status
Status
Data
Data
Data
Data
Data
Data
PNX15xx/952x Series
Control
Master
MMIO
Slave
DMA
© NXP B.V. 2007. All rights reserved.
MTL
Bus
DCS
Bus
Memory
CPU
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